I want to know how this part (matching network) is designed. Can I use simpler design with minimum components? It is an SYN470R.
If you read the chip's data sheet you can find its input impedance at 315 MHz on page 14.
You can then model that as a 12 Ω resistor in series with a 3.12 pF capacitor. If you assume a quarter wave monopole antenna, it has an output impedance of 37.5 Ω + 23.8 pF in series. Then, model both and do a simulation: -
Then run an AC analysis and you get this: -
So, it's not quite perfect at 315 MHz but, it's not far off. The gain is ~4.4 dB (not too shabby). Maybe it could be tweaked to optimum (12 dB gain) and maybe, if you took into account PCB board capacitances, self-resonant frequencies of the inductors used, it might be better than 4.4 dB of gain.
But, it's also likely that an antenna formed as a PCB pattern is going to have different impedances than for an ideal quarter wave monopole hence, you'd have to do some digging around to find more appropriate values.