In this scenario there is a clock source that shall generate 120MHz clock. This shall go into an FPGA and an ADC. When the ADC is actually transmitting data and not in a power down state, it shall transmit parallel data with a clock signal to the FPGA i.e source synchronous parallel transfer. The clock output by the ADC on this data transfer is 120MHz as well.
Now, we have the FPGA design running at 120MHz and also have ADC source synchronous interface sending data at 120MHz. The primary issue is that, from what I susptect, the region where the ADC data is being registered inside the FPGA, the two clocks inside the FPGA will not be aligned. Also, they will have a different amount of jitter on them.
Now I need to understand how to deal with this problem so data is correctly registered into block RAM in the FPGA and no data corruption occurs.
- Is it true that a clock crossing FIFO is not required in this case?
- I will certainlg need to specify timing constraints for the FPGA since the ADC clock coming in is basically a write clock for the block RAM. What SDC constraints do I use for this and what values go into the constraints?
- The two clocks will be out of phase and have different jitter but I don't think I can predict the precise amount. Do I then use an internal FPGA PLL to align the two clocks? What settings do I provide to it?
- The primary issue is not knowing the phase difference between the two clocks practically. What is the proper way to mitigate this? I believe I will need some input from the PCB design team to know length and associated propagation delay of clock signal paths.
I just want to understand the proper way to deal witn this design problem.