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What is the relevance of the left 470pF capacitor coupled to the receiving antenna in this circuit (here the site where I found it):

enter image description here

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  • \$\begingroup\$ Is your antenna wire outside? If so, it can be charged up by mist, rain, snow, or just a nice sunny day. With no capacitor, antenna current will flow through the 1M resistor, creating a DC voltage on the FET's gate, possibly destroying it, more likely just changing its drain/source current. You likely want the FET gate to remain near zero volts - set by that 1M resistor. Not so much a problem with indoor antenna. \$\endgroup\$
    – glen_geek
    Oct 13 at 23:04
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That circuit won't work without proper biasing of the NPN transistor shown in the diagram. You could put the R from collector to base; likely better (more gain) using 100k, although that will then consume about 100 uA from the 9 V supply.

The actual transistor suggested (MPF102) has an IDSS (current with VGS==0) up to 20 mA -- it will drain your 9 V battery very quickly. Putting 4.7k in the source will limit current to a more reasonable value. Putting 100 pF in parallel with that will improve VHF gain.

Actually the MPF102 is not well suited for a battery-operated device. The NTE would be much better and not need the extra components.

The 470 pF is to isolate any DC signals (including DC shorts to GND) on the antenna. Its value is not critical.

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  • \$\begingroup\$ Also, makes me wonder about the correctness of that circuit overall, given that the transistor mentioned is a FET, yet the schematic shows a BJT. Carelessness. \$\endgroup\$
    – SteveSh
    Oct 14 at 0:28
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The antenna RF is AC-coupled to the biased junction and amplified by the circuit. The cap blocks any lower-frequency DC that might get coupled to the antenna, such as power line noise or static buildup, either of which could disrupt the high-impedance bias and distort the signal.

There's a mistake however. Their diagram is wrong. The MPF102 is a JFET, not an NPN transistor. That's why the input is tied down to 0V with the 1M resistor: to bias the JFET in small-signal linear mode (this particular JFET is designed to do this.)

A transistor on the other hand needs to be biased in its linear region with the base-emitter voltage somewhere closer to 0.7V.

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