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When designing a power supply for a digital circuit such as a CPU or microcontroller, you often want to ensure that the supply does not exceed some threshold when the load is switched from minimum to maximum and vice-versa. You can call the maximum change in the output voltage caused by a load transient \$\Delta V_o\$.

\$\Delta V_o\$ will increase as the rise/fall time of the load transient also increases. When the load is a high-speed digital device, how do you determine what the rise/fall time of the maximum load transient for the power supply will be? This will help you determine what \$\Delta V_o\$ will be to make sure it does not exceed the safe supply threshold.

Should you assume the worst case would be the device driving all outputs high at the same time, meaning the load transient rise time is the same as the rise time for the drivers?

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Generally the maximum load transients occur when the CPU becomes active or inactive (e.g. POR).

Load transients generated from IO transitions are temporary and not any more severe than connecting some 10's of pF directly to VOUT.

There are three aspects to load transient response.

One is the control loop bandwidth -- this is probably << 200 kHz and therefore only helps for transients that occur over timescales of microseconds.

Secondly, the output bulk capacitor (perhaps 100's of uF) maintains the output voltage for shorter timescales (perhaps to << 1 us). This capacitance has significant parasitic inductance, and so the 3rd element is needed:

Lastly, for MCU-caused fast load transients (in the 10's of ns range), decoupling ceramic capacitors (0.1 uF to 10 uF), placed very closely to the load (MCU) maintain the output.

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  • \$\begingroup\$ Thank you for the answer, this was very helpful. \$\endgroup\$ Oct 14, 2021 at 21:11
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The case you’re referring to, a load step in the positive direction, will have an overshoot that is determined by the rate of increase, the amount of bulk bypass, and the power supply control loop.

How to determine that load step when the chip changes power states? You’ll probably have to ask the chip vendor, or characterize it yourself using a current sensor.

In any event, your worst case design will need to account for the overshoot such that the resulting voltage doesn’t exceed your max VDD level, yet allow good enough transient response so that your minimum VDD is also met during the regulator’s response time. Unsurprisingly, there’s a tuning trade off between the two, not to mention ensuring control loop stability.

But even before you get there, certain power supply types have better transient response than others. Linear is the best, followed by constant-on-time (COT) switching. Also, higher switching speed is better, but has some trade-off in efficiency, and is also limited by the stepping ratio.

Really high current supplies, like those for big CPU and GPU cores, use multiple phases which increases the effective frequency while spreading the load over multiple inductors.

Regardless, best practice is to model the power supply behavior using simulation, using your best estimate of the load step. Then you will have a better idea of how well your solution will meet your margins.

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