A long while back I read "PCB EMC Design Techniques" by Mark Montrose, and I think it's still a good read.
At the heart the current loop impedance is important, and that includes the inductance induced by the traces that are created specifically to guarantee that the capacitor's charge is mainly used for the IC it is decoupling. Those traces can actually decrease performance.
Mark Montrose writes "Maximizing the physical width of the connection from the capacitor to planes minimizes total loop inductance". Vias add inductance as well.
So in the general case, for high frequency decoupling purposes, I'ld prefer a plane connection rather than dedicated traces. The current will "find" the shortest loop anyway.
However, there is one case where I added a dedicated trace for decoupling, and it was actually a "low frequency" issue.
I had a circuit using an SDCard used to store the results of several measurements. As far as I remember, tthe SDCard was disturbing the circuit when it was switched on caused disturbances on the measurements where we were looking for very small changes in the values.
So I ended up adding a bead, and a nettie to be able to route separate VCC and GND traces up to the SDCard directly from the LDO's output.
You can see the adjacent traces on the PCB, the GND trace running up to C33 and the VCC trace up to L3.
The LDO is on the other side of the board in between the two holes on the left of "SHDN" in the white square.
It's from that area that the traces lead up to the SDCard.
IHMO this was a low frequency "bulk" capacitor issue rather than a HF decoupling issue.
This technique essentially consists in creating areas with a local ground plane. This is something that our design group used to do. More for historical reasons than any proof that I have seen. Typically, the oscillator circuit would have a local ground plane separated from the rest of the circuit except for the small area ("bridge") where all signals pass (in particular power, gnd and clock signal).
This discipline is helpful in helping avoid tracing any critical signal lines below or near the clock lines, but it's not sufficient. We ran into major disorders when the analog green video line was next to the clock line for about 10 centimeters. Everything worked fine until we went asynchronous at which point the crosstalk came in.
Increased current loop to avoid malicious currents
I've also experienced a practical case where we had a daughter board, with plenty of decoupling capacitors on it, but only a few undistributed GND connections to the main board. The return current resulting from the output changes did not follow the GND path, but used the signal lines instead, resulting in 2Vpk-pk changes on those. 0's became 1's and vice-versa at wrong times.
I improved that by recreating a GND plane connection with the main board, before resolving the issue by replacing the clock connection with a twisted wire.
That increased the current loop for the return current, so that the clock signal stayed clean. The rest didn't matter anymore as all outputs change after the clean(ed) clock and stabilize before the next clock cycle. Our prototypes were fixed just by adding this twisted wire in place of the clock connection of the connector.
There much more to tell, but well, that's why there is at least one book, several courses, etc. ;-), and practice!