This cable 1 works fine to power a PCIE accelerator device (Intel N3000-N FGPA PAC) on Dell PowerEdge R720. The power connector that plugs into the riser seems to break power cable/port standards/conventions. This led to a lot of trouble for us when we decided to plug in the FPGA in a different server. I wanted to confirm if indeed Dell breaks the convention/standard.
Figure of the end that plugs in to the Dell server riser:
From this figure, we can see that pins 1,4,6,7 on the board must be square holes. We can also see that the yellow wires (assuming +12V, see below why this assumption is correct) are away from the notch (i.e. pins 1,2,3 are +12V).
The keying 1,4,6,7 square holes matches a CPU power port (the pinout does not). While the pinout 1,2,3 12V matches a PCIE power port.
For reference the keying and pinout of standard CPU (EPS12V) and PCIE power ports are here:
The cable is advertised as 8 pin CPU to 6/8 pin PCIE power cable. The 6/8pin PCIE end conforms to the standard. The CPU end which plugs into the motherboard has the keying/shape of the CPU port but the reverse wiring/pinout (i.e., wiring is as if it was a PCIE power port).
If indeed Dell mixed the standard. WHY WOULD THEY DO THIS? WHAT MOTIVATION DID THEY HAVE?
Why yellow wires must be 12V:
This is the figure for the other end (6/8 pin PCIE) of the same cable:
We can see that wires away from the notch (pins 1,2,3) are yellow. The FPGA documentation (page 8 of 5) clearly mentions pins 1,2,3 are 12V. Since the NIC works fine with this cable, it would mean that its getting the right power supply and so the yellow wires (1,2,3) must be 12V.
Edited: For more clarity, please refer to the image here:
NOTE this image shows ports (female) not cables (male). The pin numbering is mirror image of the reference above which shows cables instead of ports.
