I am looking at a datasheet of a level converter (https://www.ti.com/lit/ds/symlink/txs0108e.pdf?ts=1634046719564&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTXS0108E - TXS0108E8) and it says it has

Maximum data rates – 110 Mbps (push pull) – 1.2 Mbps (open drain)

Does 1 bit corresponds to 1 clk cycle and then 1bps = 1 Hz in this case?

Another question is about the push pull. I am not sure I understand. Do I need to have an inverter at the outputs? I need to work at 20 MHz, meaning the voltage from 3.3V to 5V and vice-versa will change at this frequency. The input of my circuit is a clk signal that will be delayed by the delay lines.

enter image description here

  • 1
    \$\begingroup\$ 1m cable is @ 50 Ohms? and 5 ns delay? Why do you have 250 ps delay lines. $$ $$ What is your signal integrity spec? expectations? Your choices don't make sense yet tinyurl.com/ygv78f8t Notice I added parastic C, ESL and trace E looks much better than my simulation of yours. \$\endgroup\$ Oct 15, 2021 at 20:12
  • \$\begingroup\$ It seems you will have computational delays and many other delays ? What are you trying to accomplish doing this? This is NOT how to generate quadrature signals NOR phase lock 2 clocks. Say what you are trying to do at a higher level rather than this. \$\endgroup\$ Oct 16, 2021 at 14:02
  • \$\begingroup\$ Is this a BER test set? a QPSK simulator , a phase margin analyzer, a coherent QPSK demodulator or what? too many assumptions will cause unintended failures... \$\endgroup\$ Oct 16, 2021 at 14:25
  • \$\begingroup\$ TY for info. What is the pulse rate of Laser? slow? fast? Does MCU clock stability matter? or just delay time from Shot_W rising edge to leading edge of Laser pulse. What is range of delay error to be corrected from 820 ns? and preferred error tolerance? +/- x? ? \$\endgroup\$ Oct 16, 2021 at 19:27
  • \$\begingroup\$ If the pulse delay error is < 5ns=1/20MHz Why not have a circuit that detects and nulls this error with an analog servo-electronics? e.g. high speed diode and phase delay loop. Also I think this level shifter is not needed. The DS1023 may work with 3.3V input on Vdd=5V +/-0.1 \$\endgroup\$ Oct 16, 2021 at 20:10

2 Answers 2


There's 2 bits per Hz, that is, the double-data-rate throughput. So a device specified as 110Mbps will have a bandwidth of about 55MHz. So this device should be adequate for your 20MHz single-data-rate application, but mind the inserted turn-around delay.

'Push-pull' operation only means that the driving device drives both high and low. This is typical of most GPIOs. This is differentiated from an 'open collector' or 'open drain' driver that only drives low and requires a pull-up to make logic high (I2C bus for example.)

  • \$\begingroup\$ So If I understand correctly, in my case is push pull since my input is a clk source right? I am confused because open drain would fix the value at vdd or gnd, so I don't understand why there is a bit rate for open drain if the voltage is fixed by the pull up or down resistor. \$\endgroup\$
    – Raphael
    Oct 15, 2021 at 19:20
  • 2
    \$\begingroup\$ Yes, your clock source is push-pull and needs no pullup. Open drain requires a pull-up. For this translator, it needs to be on the driver side, as the translator needs to see the signal make a 0-1 transition to activate the active pull-up on the higher-voltage side. This transition will be slower than push-pull, so the achievable bit rate will be slower. \$\endgroup\$ Oct 15, 2021 at 19:28

For NRZ data is takes 2bits 01...01 to make 1Hz so 2MBps = 1MHz

The ratio of pulse width is 30:1 is also the ratio of On R to OFF R pullup means push-pull with low R in each swing is what you need for > 1 MHz.

To optimize this, the traces , cable ,should be matched to minimize reflections if the path length is > 10% of a wavelength at 2e8 m/s for a dielectric constant of 4 for epoxy and plastic insulated cables. If not terminated then there is overshoot for that path length but matched at source so minimal reflect at source. But terminations of 4k dampens the ringing somewhat without drawing too much power. These are tradeoffs.

These use high input impedance so ringing does occur but as long as that decays before the trailing clock edge resamples the data, integrity is preserved. So improve integrity in other systems, (Canbus, RS485 etc) a matched load, is used but then more power is dissipated and the Voltage is reduced 50% but without (as much) overshoot. Here the comparator or inverter threshold should be 50% of the final 4k loaded or initial voltage, which from 400 Ohms is only 11% drop in voltage.

So the level conversion must consider these factors of path length and output and load capacitance with the driver Rs to optimize signal integrity. When there is no skew between clock and data and no matched load , overshoot and ringing decay occurs from the ESL equivalent path inductance and parasitic or line capacitance such that \$Z_0=\sqrt{L/C}\$ for the desired link. This ought to be chosen to match the source RdsOn which is not given and that reduced with higher output Vdd. For 5V CMOS drivers this can often vary from 66 Ohms for low Vdd to ~ 12 Ohms for max Vdd and sometimes series R is added in these cases to match the cable or trace impedance to reduce the reflections at source for long echo times. But this IC has higher Ron values " (on the order of 300 Ω to 500 Ω) " (You might be able to correlate this R from rise/fall times from C given.) so this is designed for traces and cables in this range of impedance.

A complete spec of path length and impedance ought to be determined if you wish to optimize signal integrity and immunity from stray noise in your design to choose the best match at source. This can be simulated if you need more explanation after you detail your objectives for level conversion with ambient noise and path length.

Simulation with modifications . Better results do not use this IC. Trace E enter image description here

  • \$\begingroup\$ Thank you for your explanation. I have an instrument that will provide a 20 MHz clk, my microcontroller will use the clk of this instrument since I need both to be in phase. I will use the dealy line to change the phase between the instrument providing the clk and the microcontroller. I will use a 1 m cable from the instrument to the delay lines and another 1 m cable from the delay line to the microcontroller. I will try to better understand your answer, since it is too complex for my current knowledge, so I need to read about the terms you mentioned here. Thanks again. \$\endgroup\$
    – Raphael
    Oct 15, 2021 at 19:25
  • \$\begingroup\$ This is not a perfect model tinyurl.com/ygedgth9 But is a cable of 400 Ohm, when you add parasitic C load it gets worse. When you change the cable to 100 Ohms , it gets worse. but Prop time is 5ns/m with 1st echo at 10% of 20MHz and 2nd echo at 20% of cycle, so This IC is not ideal for typical UTP or STP cable. \$\endgroup\$ Oct 15, 2021 at 19:38
  • \$\begingroup\$ Note on page 18 they agree with me that "maximum data rates in the data sheet assume that the output impedance of the external driver is less than 50 Ω" So I would ask you to define your signal integrity specs and assumptions for impedances on source, cable and load and phase coherence and make anew question or update this one. \$\endgroup\$ Oct 15, 2021 at 19:41
  • \$\begingroup\$ Regarding to initial delay, I don't care as long as the signal is stable after some time. The scenario is the following. I send a command to the delay line, the clk is delayed by 250 ps, I do some operations in my MCU and evaluate the results. I delay the clk again, evaluate again ... until I get 360 degrees (total of 50 ns delay). So at each 250 ps I perform some analysis in the MCU. Regarding signal integrity, the clk signal from the instrument A to delay line to MCU must be good enough to be used as the MCU clk. Cable is BNC or SMA. \$\endgroup\$
    – Raphael
    Oct 15, 2021 at 20:32
  • \$\begingroup\$ How many MCU cycles in 50ns? (1?) 250ps is useless \$\endgroup\$ Oct 15, 2021 at 22:12

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.