TXS0108E8 Specification in Mbps, what is the equivalent in MHz?

Question

I am looking at a datasheet of a level converter (https://www.ti.com/lit/ds/symlink/txs0108e.pdf?ts=1634046719564&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTXS0108E - TXS0108E8) and it says it has

Maximum data rates – 110 Mbps (push pull) – 1.2 Mbps (open drain)

Does 1 bit corresponds to 1 clk cycle and then 1bps = 1 Hz in this case?

Another question is about the push pull. I am not sure I understand. Do I need to have an inverter at the outputs? I need to work at 20 MHz, meaning the voltage from 3.3V to 5V and vice-versa will change at this frequency. The input of my circuit is a clk signal that will be delayed by the delay lines.

Answer 1

There's 2 bits per Hz, that is, the double-data-rate throughput. So a device specified as 110Mbps will have a bandwidth of about 55MHz. So this device should be adequate for your 20MHz single-data-rate application, but mind the inserted turn-around delay.

'Push-pull' operation only means that the driving device drives both high and low. This is typical of most GPIOs. This is differentiated from an 'open collector' or 'open drain' driver that only drives low and requires a pull-up to make logic high (I2C bus for example.)

Answer 2

For NRZ data is takes 2bits 01...01 to make 1Hz so 2MBps = 1MHz

The ratio of pulse width is 30:1 is also the ratio of On R to OFF R pullup means push-pull with low R in each swing is what you need for > 1 MHz.

To optimize this, the traces , cable ,should be matched to minimize reflections if the path length is > 10% of a wavelength at 2e8 m/s for a dielectric constant of 4 for epoxy and plastic insulated cables. If not terminated then there is overshoot for that path length but matched at source so minimal reflect at source. But terminations of 4k dampens the ringing somewhat without drawing too much power. These are tradeoffs.

These use high input impedance so ringing does occur but as long as that decays before the trailing clock edge resamples the data, integrity is preserved. So improve integrity in other systems, (Canbus, RS485 etc) a matched load, is used but then more power is dissipated and the Voltage is reduced 50% but without (as much) overshoot. Here the comparator or inverter threshold should be 50% of the final 4k loaded or initial voltage, which from 400 Ohms is only 11% drop in voltage.

So the level conversion must consider these factors of path length and output and load capacitance with the driver Rs to optimize signal integrity. When there is no skew between clock and data and no matched load , overshoot and ringing decay occurs from the ESL equivalent path inductance and parasitic or line capacitance such that \$Z_0=\sqrt{L/C}\$ for the desired link. This ought to be chosen to match the source RdsOn which is not given and that reduced with higher output Vdd. For 5V CMOS drivers this can often vary from 66 Ohms for low Vdd to ~ 12 Ohms for max Vdd and sometimes series R is added in these cases to match the cable or trace impedance to reduce the reflections at source for long echo times. But this IC has higher Ron values " (on the order of 300 Ω to 500 Ω) " (You might be able to correlate this R from rise/fall times from C given.) so this is designed for traces and cables in this range of impedance.

A complete spec of path length and impedance ought to be determined if you wish to optimize signal integrity and immunity from stray noise in your design to choose the best match at source. This can be simulated if you need more explanation after you detail your objectives for level conversion with ambient noise and path length.

Simulation with modifications . Better results do not use this IC. Trace E