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The question is that I have 3 inputs (X,Y,Z) and two outputs (S,C). I have to implement a full adder circuit using only AND-XOR gates. I did a little bit of research but I couldn't figure out a way to implement it using only the given gates. Here is an screenshot of a full adder circuit. The only problem with this implementation is the OR gate. enter image description here

Is it possible to implement a full adder using only AND-XOR gates? If possible any help will be appreciated.

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  • \$\begingroup\$ If you add a link to your logic simulation - it looks like one of the many online simulators - then others can play around with it and maybe offer you some help. Edit the link into your question. Don't hide it down here in the comments. \$\endgroup\$
    – Transistor
    Oct 15, 2021 at 21:28
  • \$\begingroup\$ No i didn't use any online websites. I designed this in Logicly and just took an screenshot. \$\endgroup\$
    – Sahar
    Oct 15, 2021 at 21:35
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    \$\begingroup\$ logic.ly/demo is an online simulator. If you use that and provide a link then we can all play with it. \$\endgroup\$
    – Transistor
    Oct 15, 2021 at 21:44
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    \$\begingroup\$ Well, you could research ways to make an OR gate out of what you have. (NB : it doesn't have to be elegant!) \$\endgroup\$
    – user16324
    Oct 15, 2021 at 21:46
  • \$\begingroup\$ Here is the link ufile.io/khlrxo7s \$\endgroup\$
    – Sahar
    Oct 15, 2021 at 22:03

2 Answers 2

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You already got the S output.

Tips:

  1. Can you make an inverter (one input and one output) using a XOR and connecting one of the inputs to a fixed level?

  2. You can make any circuit using NANDs, right?

As @user_1818839 said, it doesn't have to be elegant!

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  • \$\begingroup\$ No thats the problem. The only gates i have to use are XOR-AND gates. \$\endgroup\$
    – Sahar
    Oct 16, 2021 at 6:12
  • \$\begingroup\$ Well, figure out if either of those can be used as an inverter! \$\endgroup\$
    – user16324
    Oct 16, 2021 at 20:51
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You can create an OR gate if you invert the inputs and outputs of the AND using XOR gates wired as inverters. That's inelegant but it works.

That’s just one way, there are others. A hint: a full-adder is realizable as a pair of cascaded half-adders.

Another hint: Why is the last carry block's gate in a full adder an OR gate (and not a XOR)?

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  • \$\begingroup\$ Can you please provide an screenshot of your implementation? \$\endgroup\$
    – Sahar
    Oct 15, 2021 at 21:37
  • \$\begingroup\$ @Sahar Welcome to EE.SE. As you will probably note from now on, we use the Socratic Method for this type of question. You may update your question to show your progress or how you are stuck after trying to apply the tip given here. \$\endgroup\$
    – devnull
    Oct 15, 2021 at 21:45
  • \$\begingroup\$ I guess i have to study more about this method before solving this question. \$\endgroup\$
    – Sahar
    Oct 15, 2021 at 21:56
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    \$\begingroup\$ @Sahar. It just means we won't provide the final answer but will be glad to help you find it. \$\endgroup\$
    – devnull
    Oct 15, 2021 at 21:58

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