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I am trying to blink an LED on a new board I bought that uses an Artix-7 FPGA. This is my first time using Vivado and for some reason when I run a simulation for 1 second the simulation draws the waveform very slowly and increments in steps of 2ms. This means that a 1 second simulation is taking me up to 4 minutes to complete.

The way I am running the simulation for 1 second is by setting the "Run for" box at the top of Vivado to 1 second and then hitting "Run All."

Has anyone run into this issue before or know why Vivado is simulating so slowly?

Here is my HDL code to generate a 1Hz blinking LED from a 200MHz clock signal:

module blinking_LED( clk, divided_clk );
input clk;
output divided_clk ;

wire clk;
reg divided_clk = 0;

localparam div_value = 99999999;
//<statements>
// division_value = 200MHz/(2*desired_value) - 1
integer counter_value = 0;
// counter 
always@ (posedge clk)
begin
    if (counter_value == div_value)
        counter_value <= 0;
    else 
        counter_value <= counter_value+1;
end 
// clock divider
always@ (posedge clk)
begin
    if(counter_value == div_value)
        divided_clk <= ~divided_clk;    // Suppose to occur after 0.5sec
    else
        divided_clk <= divided_clk;     // If the counter is not at its limit, do nothing 
end
endmodule

Here is the testbench I am using:

`timescale 1ns/100ps

module blinking_LED_tb;
reg clk ;                   // input
wire divided_clk;           // output 

initial 
begin
    clk = 0;

$stop;
end
//////////////////////////////////////////////////////////////////////
// Clock Driver
//////////////////////////////////////////////////////////////////////
always 
#2.5 clk = ~clk;

//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  blinking_LED
//////////////////////////////////////////////////////////////////////
blinking_LED blinking_LED_0 (
    // Inputs
    .clk(clk),

    // Outputs
    .divided_clk(divided_clk)

    // Inouts

);

endmodule

Here are my simulation settings: enter image description here

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  • \$\begingroup\$ Your clock period is 5ns (200MHz). But you are simulating with time steps of 1ns or 100ps...for one second. Step back and think about that. Do you really need 200 million data states? And on top of that do you really need five time steps per data state? \$\endgroup\$
    – DKNguyen
    Oct 16, 2021 at 5:01
  • \$\begingroup\$ That's pretty good for digital logic simulation. I've had 3 second simulations take several hours, but of course that wasn't just blinking a LED. \$\endgroup\$
    – user16324
    Oct 16, 2021 at 13:11

2 Answers 2

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Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation.

One trick you can do is speed up your blink rate just for the purpose of simulation, say to 100 Hz. Then you'll be able to verify your code oscillates correctly in a mere 10ms simulation.

Once it works, change back to 1Hz and run one long simulation to confirm it still works. This avoids having to run slow 1 second sims to debug your code.

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F = 200 MHz or T = 5 ns is the fastest clock in your design and it looks like you don't have any events in your design to be captured at 100 ps precision. You can run simulation with a precision of 500 ps instead of 100 ps, since your Test bench needs to drive clock edges at 2.5 ns. This may speed up the simulation. But the difference may not be noticeable for simpler designs.

Also, if you don't want to look into internal signals anymore, but just the top level ports of a module, you can set debug level to OFF in elaboration settings in Vivado. This is particularly useful at system level simulation where the design is complex and you are confident that submodules need not be debugged anymore. You can run simulations very fast in this way.

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