High frequency BLDC control for parallel speed and position control. Looking for thoughts

Question

I was not able to find a similar topic but am kind of stuck with my problem.

What am I doing?

I am trying to control the speed of a BLDC Motor very precisely but have to control the position of the spinning motor shaft while rotating.

On the shaft a disc is installed with two slits shifted 180 deg from each other. I need to be able to synchronize the position of the slits to an external signal of 5 Hz and then keep spinning with a constant speed of 150 RPM.

I am using a PLL Loop on an FPGA to determine the phase shift of the motor which is controlled via PID and working fine. The phase shift is determined 20 times per revolution from an AB-encoder signal which gives a control frequency of 50 Hz. The PLL on the FPGA generated a PWM signal which is resolved by an ESC and controlling the BLDC.

The motor is spinning now at a constant speed of 150 RPM with sufficient jitter. For the position control I am using the signal of the X-encoder which is generated once per rev. I am now synchronizing the X-encoder to the 20 AB-encoder brackets.

I tried now to simply delay the signal of the X-encoder by an specific amount of time, to have create positioning of the slit on the spinning disc. However, with this logic I am only able to delay the position of the slit in the matter of (1/20) of the disc, because of the other signal from the AB-enc. I should be able to position the slit position from -180 to +180 degrees compared to the external 5 Hz signal.

Has anyone experience with such a parallel position and speed control of a BLDC?

Answer 1

Without knowing your details on ESC voltage , power, kRPM/V, motor size, gear ratio or slot width, I made some assumptions and modelled the performance using a type II mixer used in the CD4046 PLL with results show below.

The use of the 50 Hz A-B encoder is disruptive to the loop since it is the wrong phase / frequency reference.

The phase control that I chose was the duty cycle of the I1 pulse using some reference not shown and varying the positive edge delay or duty cycle. This is one of the side panel sliders.

In your case it could be done digitally with a 10 bit counter and frequency multiplier with the divider locked to 5 Hz or in analog with a sawtooth and analog comparator to shift phase of the index pulses. (2 slots or even BLDC pulses)

But there are many other ways.

If you wanted smaller phase-jitter you might use a 1000 p/rev encoder with an index pulse (1 slot) with a dual mixer for velocity (RPM or ppm) and position (phase).

If you can imagine it, you can simulate it,

Answer 2

I don't know about your PID, but you better change it to cascaded P (position) and PI (velocity controller)

^{simulate this circuit – Schematic created using CircuitLab}

In a first phase you do match the velocity. You do use a trajectory planner with a velocity output that ramps from 0 to target velocity. At this point the Kp of the position controller is 0.

Note that your encoder resolution is not that big to make any good positioning, further it has 20 pulses/rev instead of having 2^N pulses which would simplify the calculations, since the we use base number of 2 in computer world. But let's say you do count these AB pulses with a N-bit counter, so there is an overflow at the end. Somewhere you should have a zero marking on it, but you didn't describe this, let's suppose that at certain moment you do reset the counter to zero and that means the reference position.

EncPulses = ReadCounterValue();
DeltaPulses = EncPulses - EncPulsesOld;
EncPulsesOld = EncPulses;
Vact=DeltaPulses/dT;

Position = (Position + DeltaPulses + 3*M/2) %M - M/2;

The Position will be output in your case where modulo (M) is 20 the value from -10 to 9.

You do the same for a PLL pulses, where you should have a signal that outputs exactly M pulses between one revolution. Then you attach this PLL position to input of the cascaded block and enable the P controller by setting a correct Kp value.

It could be even simplified by using a first order lag on velocity setpoint and you feed setpoint position directly from PLL position (with KP being non-zero), since the position error would fluctuate from +max to -max upon filtering out it would give zero mean value. Only when velocities would become near equal it will lock-in.

^{simulate this circuit}