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Currently I am learning about decoupling circuits for noise suppression and decoupling of digital ICs. I know about L-type circuits containing a capacitor in parallel and a ferrite bead in series as well as π-type circuits which contain two parallel capacitors and a ferrite bead in series between them.

Now I was wondering which values I need to determine which of those circuits can suppress noise better?

So, let’s get started! What is noise? For my understanding noise defines high frequency signals. To prevent these signals in my circuit I would need low pass filters, so the impedance of the circuit is relevant. But is it really as easy as measuring the impedance?

I know that this is a huge topic and there is not just one answer. But maybe you can give me some hints to get a better feeling / understanding of what good characteristics for noise suppression filters are.

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    \$\begingroup\$ hottconsultants.com/techtips/decoupling.html, or more generally, hottconsultants.com/tips.html Or just buy his book. \$\endgroup\$
    – DKNguyen
    Oct 16 at 21:57
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    \$\begingroup\$ You can also use an inductor in place of a ferrite bead, though for noise filters ferrite beads are probably better. \$\endgroup\$
    – Hearth
    Oct 16 at 22:00
  • \$\begingroup\$ @Hearth Or low value resistors (<5Ohm), which are safest if you have no idea what you're doing. \$\endgroup\$
    – DKNguyen
    Oct 16 at 22:37
  • \$\begingroup\$ H Ott was the Godfather of EMC , I read his book many times in the late 70s' early 80s' dignitymemorial.com/en-ca/obituaries/livingston-nj/… It is a must read for all EE's \$\endgroup\$ Oct 16 at 23:17
  • \$\begingroup\$ @DKNguyen why is a low value resistor better than a ferrite bead? Wouldn't a ferrite add an additional -20db/decade? \$\endgroup\$
    – F_Schmidt
    Nov 5 at 17:44
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"Decoupling networks" are just a part of denoising the Power Delivery Network (PDN) as it is termed by Intel and Altera. They may consist of many variations of RLC passive components including the distributed low inductance of power/ground planes and high capacitance from the small gap where \$Z_0=\sqrt{\frac{L}{C}}\$

I would like to show how a simple example with almost 60 dB of denoising 50 MHz clock noise with a simple C across a single CMOS inverter, but with some realistic ESR, ESL and RC values for edge noise from the crossover conduction of a simple CMOS Pch+Nch with Vt=1.5V such that at Vgs=2.5 both FETs are already partially conducting with some junction Q = CV loading the supply.

What it means is schematics are just logic diagrams but do not show the realistic noise above 10MHz from CMOS nor induced line noise from high impedance or magnetic induction.

The schematic of 2 CMOS inverters does not show it as it really is.

Here the noise generator, which is a simple high speed CMOS inverter with an effective inductive trace of a bit more than a cm on each rail with internal Ciss and Coss and Miller capacitance. I added an ideal switch with a decoupling cap to show the attenuation of Vpp when you add the cap with a switch.

enter image description here

For more detailed background references;

AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design (PDN)

PCB decoupling scheme : Frequency Domain Target Impedance Method (FDTIM)

Altera PDN Tool User Guide

Intel FPGA Powerplay & denoising summary , Quartus notes

enter image description here

PDN Summary
https://www.intel.com/content/www/us/en/support/programmable/support-resources/signal-power-integrity/power-distribution-network.html

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What is noise?

In most general terms, noise is any undesired signal.

Power supplies are commonly modelled as ideal voltage sources. For logic or small-signal analog circuits, it's a DC voltage source. It has no variations from the desired voltage. Note that some circuits require two sources, and some even more. So

For my understanding noise defines high frequency signals.

is close. Usually, it's technically any AC signal which is undesired. In logic circuits, high-frequency transients are the biggest source of problems, but in part that's because getting rid of low-frequency components is so easy. Except when it's not. For instance, when making ultra-high-impedance amplifiers (at pA levels) it's easy to get leakage currents from DC components which affect an amplifier, and which require measures such as guard rings. Extreme cleanliness can come into play in such circuits, and a fingerprint on a pc board can cause problems. Even logic circuits can occasionally have problems when using CMOS (high impedance inputs) and failing to clean solder flux from a board after working on it.

But, for instance, in audio systems the biggest source of noise is usually power line frequencies - 50 or 60 Hz and harmonics.

To prevent these signals in my circuit I would need low pass filters, so the impedance of the circuit is relevant. But is it really as easy as measuring the impedance?

Well, sort of. But do you have any idea how hard it is to accurately measure impedance at high frequencies? You need to become familiar with the concept of parasitic components.

Additionally, there are such things as external sources which can be picked up by antenna effects, and there are issues such as ground loops which can cause real problems. If two conductors run side-by-side and one contains an AC signal, the other conductor will to some degree intercept the radiation from the first conductor, and this will produce what is called cross-talk, and which can be very difficult to track down. Trust me on this.

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This Murata guide is a good starting point: https://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx

What is noise? Mostly, it’s switching transients being kicked onto the power rails. The job of a well-designed power supply is to provide very low impedance to the IC and thus minimize the impact of these switching transients.

The tl, dr version is that you can block the noise using inductance or lossy inductance (e.g., ferrite), but in most cases the heavy lifting is done by shunting the noise locally using capacitance. Often these techniques are used together, as well as careful attention to physical design and placement to get the best possible power integrity at the lowest cost in components and board area.

The key to maximizing the effectiveness of shunt (bypass) caps is understanding the concepts of loop area and parasitic inductance. A rule of thumb for high-frequency bypass is that capacitance is 1/10 as effective when placed on die, on package, near the IC on board, and at the power supply.

If your application is critical, and your project can afford it, there are power integrity tools from companies like Ansys and others that analyze your physical design to determine impedance and noise.

More here: https://www.ansys.com/products/electronics/ansys-siwave

Most designers don’t bother with this software, and instead use the time honored practice of bypassing at the power pins with lower valued caps (like 0.1uF) and use bulk caps farther away and at the power supply. Sensitive analog supplies might get ferrites to block digital noise.

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