Hi this is my first question!

So I'm clearly a beginner in electronics and studied for months, now the topic I've studying is logic gates and boolean algebra also the TTL ic. I've been curious if how can you convert a three input NOR gate as a two input NOR gate?

  • \$\begingroup\$ If I say normally you have 3 choices A , B or C but now you have only 2, how do you cancel the 3rd choice? Let that unused input = 0 or 1? \$\endgroup\$ Commented Oct 21, 2021 at 6:03

3 Answers 3


Here's the truth table for a three input NOR gate:

$$ \begin{array}{llll|l} &A &B &C &F \\ \hline &0 &0 &0 &1 \\ &1 &0 &0 &0 \\ &0 &1 &0 &0 \\ &1 &1 &0 &0 \\ &0 &0 &1 &0 \\ &1 &0 &1 &0 \\ &0 &1 &1 &0 \\ &1 &1 &1 &0 \\ \end{array} $$

The first four lines are the same as the truth table for a two-input (A and B) NOR gate. Notice that in those the first four lines, C is always low, so as long as we keep input C low, we can use inputs A and B as if this were a two input gate.

In fact, you can use any two of the three inputs, and as long as you keep the third unused input low, you effectively have a two-input NOR gate.

Think of it like this: any high input to a NOR gate will cause the output to be held permanently low. So, for a NOR gate with any number of inputs you keep unused inputs low to prevent them from fixing the output low, while using the remaining inputs normally.

For an OR gate with too many inputs, the same condition exists - all unused inputs should be held low, since a high unused input will cause the output to be held permanently high.

For AND and NAND gates, the situation is that any low input will fix the output to some state, regardless of the state of the other inputs. So, for AND/NAND you must hold unused inputs high instead, to permit the other inputs to operate normally.

Another way to approach the problem is by tying any two inputs together, to form a single input. While this works, it does mean that the new "compound" input has twice the capacitance of a normal single input, and will be ever-so-slightly slower to respond.


simulate this circuit – Schematic created using CircuitLab

Another trick you can use to reduce the IC count in your circuit, is to use a spare NAND or NOR gate in the package to build a NOT (inverter) gate:


simulate this circuit


To convert a three-input gate to two inputs, simply connect two of the inputs together.

Alternatively, you could connect the unused input to Vcc or Ground, whichever way will allow the gate to operate as required.

  • \$\begingroup\$ Running the unused input to ground (in the case of a NOR gate) will present less load to whatever's driving that pin -- and the gate itself will be an infinitesimally bit faster, probably. \$\endgroup\$
    – TimWescott
    Commented Oct 21, 2021 at 2:11
  • \$\begingroup\$ thanks for your answers I'm confused with all the logic :D \$\endgroup\$ Commented Oct 21, 2021 at 2:46
  • \$\begingroup\$ In the case of a 3-input NOR gate, do not connect the unused input pin to Vcc. If you connect to Vcc, the gate will always report the same result no matter which combination of highs and lows are on the other two pins. \$\endgroup\$ Commented Oct 21, 2021 at 3:28
  • \$\begingroup\$ It may help by recognizing that a NOR gate is an AND gate with inverted INPUT pins, that is, it will present a high output if and only if all three inputs are low. At that point, it is obvious that you tie the "third" input low. \$\endgroup\$ Commented Oct 21, 2021 at 5:11

I just realized that connecting and AND Gate to one of the three input then connecting both pins of that and gate then connect the two remaining input of the NOR gate to each other would convert it to a two pin NOR gateOther way to convert 3 input NOR gate to 2 input NOR Gate

  • 2
    \$\begingroup\$ As a general rule, you don't want to do this. Most logic families are designed to present a specified load on an input pin to the driver from the previous stage. By tying two inputs together, you double the load presented to the previous stage output. In this example, tie one of the AND gate inputs high, and tie one of the NOR gate inputs low, instead of tying them together as you did. \$\endgroup\$ Commented Oct 21, 2021 at 5:09
  • \$\begingroup\$ @JohnR.Strohm in theory you're right and the first CMOS family ever suffered from a seriously poor fanout (5-15 input max, IIRC). These days even the cheapest HC family has enough strength for at least 10 LS (TTL!) loads. The tied input NAND or XOR is the defacto inverter when you have a spare gate \$\endgroup\$ Commented Oct 21, 2021 at 5:50
  • \$\begingroup\$ The AND on the left of your circuit adds nothing to the logic, but it adds a propagation time and raises power needs in real hardware. Nobody would actually do this. \$\endgroup\$ Commented Oct 21, 2021 at 7:11
  • \$\begingroup\$ thank you so much for all the feedback much appreciated, I'll surely learn from all of you! \$\endgroup\$ Commented Oct 21, 2021 at 7:55
  • \$\begingroup\$ @LorenzoMarcantonio, you're thinking of RTL (resistor-transistor logic). Every RTL gate datasheet included fan-out and fan-in characteristics: how many "standard loads" an output pin could drive, and how many loads an input pin presented. Designers had to worry about this. This was one of the first things TTL fixed. RTL was an active logic using bipolar transistors, though. \$\endgroup\$ Commented Oct 21, 2021 at 15:23

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