I was reading about the I2C Clock stretching.
I understood like, in cases when the slave is requires some time to manage the received data from the master, it slows down the communication speed by stretching the clock SCL line.
I tried to dig deep but was not able to understand it better.
From what I believe, the slave doesn't send the acknowledgement bit to the master and that's what causes the delay. That's how the clock appears to be stretched? That's my guess. But I am not sure. Can someone clarify on how this happens?
In that case, what if the master wants to transmit another set of data to the slave during the clock stretching? Can the master do it during that time or what happens if its does? How can it transmit a new set of data when it hasn't received the acknowledge bit of its previous data that it sent?