How does data transfer work in direct memory access?

Question

http://www.unife.it/ing/lm.infoauto/sistemi-elaborazione/dispense/csf04_12.pdf

Page 2

My confusion:

1. First peripheral device sends DREQ.
2. DMAC makes HOLD=1.
3. Microprocessor finishes current machine cycle and makes HLDA=1.
4. DMAC makes DACK=1. Now DMAC is the system bus master.

How can we call DMAC the bus master when it doesn't hold data bus? Is it due to the fact that it can generate control signals we call it bus master? It controls the system bus. The processor can keep doing work that doesn't require the system bus.

Now what happens? How does data transfer from

1. Peripheral device to memory
2. Memory to peripheral device

Most books simply write data transfer occurs but don't explain this.

My hypothesis:

Say we want to write to peripheral:

DMAC gives IOW to memory, then data starts transferring from memory to peripheral device via the data bus.

Where does it write? At what location does it write? There is no address bus connected to the peripheral device.

Answer 1

In this scenario the device does not use the address bus because it has a dedicated DMA channel - the request and acknowledgement pins. So it uses one DMA channel on the DMA controller. So when peripheral sees a DMA cycle it knows it must either read or write data at the data bus, while the DMA controller drives the memory address for the memory to write or read.

In order to use DMA, the DMA controller must be set up so it knows which DMA channel is used, how much data will be transferred and which memory addresses are used for the data transfer, and also if the data direction is from memory to peripheral or from peripheral to memory. The peripheral must also be set up to make it ready for DMA transactions, for example it might also need to know how much data will be transferred and to which direction.

So the DMA controller is the bus master as it controls the memory and peripherals to do a data transfer between them directly in a single bus operation, the DMA controller does not care what data there would be on the data bus and when it is transferred on the bus.