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My confusion:

  1. First peripheral device sends DREQ.
  2. DMAC makes HOLD=1.
  3. Microprocessor finishes current machine cycle and makes HLDA=1.
  4. DMAC makes DACK=1. Now DMAC is the system bus master.

How can we call DMAC the bus master when it doesn't hold data bus? Is it due to the fact that it can generate control signals we call it bus master? It controls the system bus. The processor can keep doing work that doesn't require the system bus.

Now what happens? How does data transfer from

  1. Peripheral device to memory
  2. Memory to peripheral device

Most books simply write data transfer occurs but don't explain this.

My hypothesis:

Say we want to write to peripheral:

DMAC gives IOW to memory, then data starts transferring from memory to peripheral device via the data bus.

Where does it write? At what location does it write? There is no address bus connected to the peripheral device.

  • \$\begingroup\$ This seems to assume only one register per peripheral. \$\endgroup\$
    – DKNguyen
    Oct 21, 2021 at 13:30

1 Answer 1


In this scenario the device does not use the address bus because it has a dedicated DMA channel - the request and acknowledgement pins. So it uses one DMA channel on the DMA controller. So when peripheral sees a DMA cycle it knows it must either read or write data at the data bus, while the DMA controller drives the memory address for the memory to write or read.

In order to use DMA, the DMA controller must be set up so it knows which DMA channel is used, how much data will be transferred and which memory addresses are used for the data transfer, and also if the data direction is from memory to peripheral or from peripheral to memory. The peripheral must also be set up to make it ready for DMA transactions, for example it might also need to know how much data will be transferred and to which direction.

So the DMA controller is the bus master as it controls the memory and peripherals to do a data transfer between them directly in a single bus operation, the DMA controller does not care what data there would be on the data bus and when it is transferred on the bus.

  • \$\begingroup\$ Say I want to do IOW (eg print) via DMA. How would that work out? I will try my best to hypothesize. imgur.com/a/lEPEhCF it is a bit long so i made image. hope you won't mind that. \$\endgroup\$
    – gaznol
    Oct 22, 2021 at 14:31
  • \$\begingroup\$ You would set up a buffer with data and say to DMA controller to transfer from memory address X to DMA channel Y, and would tell the peripheral on DMA channel Y to accept data over DMA transfers. When the peripheral is ready it will request data by activating DMAREQ and when DMA controller has seen the request and negotiated being in control of bus ot will do a memory read cycle while notifying the peripheral with DMAACK and maybe with IOWR that it should now accept data. Since it is a DMA cycle as DMAACK is active the peripheral knows to ignore the address as it knows it is not an IO cycle. \$\endgroup\$
    – Justme
    Oct 22, 2021 at 15:07
  • \$\begingroup\$ Now you confused me even further. imgur.com/a/sTR86Er you confused me by saying data comes to dmac channel at first then to io. so if that is the case, how does data comes to dmac altogether? DMAC isn't even connected to data bus? \$\endgroup\$
    – gaznol
    Oct 22, 2021 at 15:30
  • \$\begingroup\$ I never said data comes to DMA controller. The memory read and peripheral write happens in same single cycle. You need to configure the DMA controller from which memory address it starts to do memory accesses. Besides obviously the DMA controller must be on data bus so you can control it and read status. Just look at how IBM PC (the original 5150) does it, the diagram very closely resembles it but is obviously simplified for educational purposes so there is not too much detail. \$\endgroup\$
    – Justme
    Oct 22, 2021 at 16:02
  • \$\begingroup\$ I am still unclear, how data is being transferred. My guess is DMAC gives control signals and data goes from Memory to IO. Other than that things don't make sense to me here. imgur.com/a/uX8dfPr here it seems to be connected with all buses. it is confusing me even more and more. i just want to know how datat transfers from memory to IO. \$\endgroup\$
    – gaznol
    Oct 22, 2021 at 16:36

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