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I am using a ProASIC3E PQ208 FPGA and Libero tool to write the vhdl code and program the board on which the FPGA is soldered. When I try to open Libero again to program file, it starts the synthesis again. The old synthesis file exists and I have not made any changes, but still there is place and route operation going on everytime I try to program the device .

I have never faced this issue when generating bitstream in Xilinx Vivado. The Actel documentation is also not that great so I could not figure out why this was happening.

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There are two potential ways to correct the issue.

  1. Create a script that after running all the required steps to generate a config. file (synthesis, place & route, and config. file generation) saves the project
  2. Try to program your device by going directly to Flash Pro instead of launching Libero SoC IDE
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  • \$\begingroup\$ Hi, thanks for the answer. I am currently using FlashPro to program the device as a workaround. I will try the first option as well, thanks. \$\endgroup\$ Nov 12, 2021 at 12:37

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