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I've designed a small circuit board with a Cyclone 10 LP FPGA and an EZ-USB FX2LP microcontroller. My current revision has a 10-pin header for connecting a USB Blaster, and it works just fine that way. However, I would like to program the FPGA using the on-board microcontroller so I can directly transfer the programming file over USB and avoid connecting the programming cable. The EZ-USB has some GPIO pins that I can connect to the JTAG pins of the Cyclone 10 LP as in Figure 97 of the Cyclone 10 LP Handbook, so in principle this should work.

At this point, I have only a rudimentary understanding of JTAG so my question is pretty broad: how does programming FPGAs via JTAG work? Is there some reference implementation of software in C that outputs the TCK, TDO, TDI, and TMS signals that I can adapt for the microcontroller? I just need some good references or keywords to do further research... I think Section 6.1.4.7 of the handbook above is the beginning of what I need, but I need some more detail and I'm not sure where to begin.

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    \$\begingroup\$ Could this be helpful: github.com/mithro/ixo-usb-jtag \$\endgroup\$
    – Codo
    Oct 21, 2021 at 15:10
  • \$\begingroup\$ @Codo looking at the readme... yes, definitely! thanks \$\endgroup\$
    – Andrew
    Oct 21, 2021 at 15:15

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Altera (now part of Intel) used to provide reference software for this. It was called Jam STAPL player. It was up to the user to port this to the target host. You may be able to find this on the internet somewhere or request access from Intel.

In order to use it, you would generate a .jam or .jbc format file in Quartus, and use that with the Jam STAPL player.

We use this capability regularly at my place of employment.

About JTAG:
TMS, TCK, and TDI are all inputs to the FPGA. They are essentially: select, clock and Input Data. TDO is output data. JTAG isn't all that complicated, but it is arcane enough that using the reference code is preferable to reinventing the wheel.

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  • \$\begingroup\$ Thanks, I'll take a look, I found github.com/margro/jam-stapl that I can use as a starting point. I'll mark this the answer if I can get it working :) \$\endgroup\$
    – Andrew
    Oct 23, 2021 at 1:13
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I realize you're looking at an Intel part and not Xilinx, but the following application note from Xilinx does a relatively good job of explaining some popular methods for in-system programming.

XAPP058

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One of the standard formats for that is Serial Vector Format (SVF). You'd use the quartus_cpf tool to convert the .sof configuration file to SVF format.

This file then describes the exact JTAG sequence. Replaying that sequence with an FX2 will require a bit of trickery if you want it to be fast, you might need to set up an extra pipeline that you can connect to TDI for the bulk download so the bitstream can bypass the 8051.

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  • \$\begingroup\$ IThanks, I did some more digging and found this myself. I wonder, could you point me to some reference on how to convert an SVF into a waveform? I don't think I need it to be fast (although maybe I'll eat my words later :) \$\endgroup\$
    – Andrew
    Oct 26, 2021 at 22:38
  • \$\begingroup\$ @Andrew, most people use an FTDI USB-to-serial converter and something like openocd for programming, the FX2 setup is kind of unusual (but that and the TUSB1210 are pretty much your only options for high-speed USB). The SVF is just text that lists the JTAG state transitions (on a high level, as instructions to go to a specific state or stay there for a number of cycles) and the data to be shifted into TDI or expected back from TDO. If you use the PAUSE-DR states, you can probably get away with a few vendor-defined setup packets for "send these bits to TMS" and "send these bits to TDI". \$\endgroup\$ Oct 27, 2021 at 9:16

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