3
\$\begingroup\$

sr-latch

In case of a NOR SR-latch, if we make S = 0 and R = 0, then output Q = 1 and nQ = 0. I also know one important rule which is if we put high input in the set line (S = 1) then output Q goes high.

If S = 0 and R = 0 then how does Q become 1? Is it like following that above rule because after S = 0 we still do not have one more input in the second gate to get nQ output. If it is not we can't have input in the first gate too,nd we aren't suppose to have output at all. Yet we have that output Q = 1.

My actual confusion is, I can't understand what the actual reason is behind Q becoming 1, and how we are getting high output with only having one input R = 0.

\$\endgroup\$
19
  • 1
    \$\begingroup\$ if we make S = 0 and R = 0. Then Output Q = 1 and nQ = 0 So are you saying that it must be Q = 1 and nQ = 0 and cannot be the opposite: Q = 0 and nQ = 1 ? Would the state of Q and nQ depend on which input was made 1 last? Realize that the essense of a latch is that can remember what happened before. \$\endgroup\$ Commented Oct 22, 2021 at 7:36
  • \$\begingroup\$ See my answer, last part electronics.stackexchange.com/questions/577071/… \$\endgroup\$
    – Antonio51
    Commented Oct 22, 2021 at 8:25
  • \$\begingroup\$ @f_chowdhury i.sstatic.net/czuEX.png If you don't understand the use of the RS-NOR K-map, feel free to ask ... (the 'system" moves vertically, the user "horizontally") \$\endgroup\$
    – Antonio51
    Commented Oct 22, 2021 at 8:43
  • \$\begingroup\$ @Antonio51 I can't understand how you made k-map for RS-NAND. I want to understand for NAND first. Why do we need to make a k-map? \$\endgroup\$
    – F.C. Akhi
    Commented Oct 22, 2021 at 8:45
  • \$\begingroup\$ for obtaining this k-map, OPEN the "return" of outputs to the inputs ... and create 2 new variables with same name except low literals ... Then fill (simulator can help ... )-: ) the k-map with the FOUR variables. You will note that there is 2 stables states in one column ( -> the fact of "memory") and 1 stable state in the others (so, no other alternative). \$\endgroup\$
    – Antonio51
    Commented Oct 22, 2021 at 8:52

3 Answers 3

4
\$\begingroup\$

Maybe it will help to take things in steps. I want to start by describing the feedback principle here, which is key to understanding what is meant by the word "latch". Let's look at two inverters, connected in a manner similar to the cross-coupled NOR gates of your circuit:

schematic

simulate this circuit – Schematic created using CircuitLab

The first hurdle is to recogise that all three circuits 1, 2 and 3 are identical. Circuits 2 and 3 are easier to follow, without the crossed wires.

In circuit 2, inverter X input is being fed with with a low output from inverter Y, so X outputs a high, as you would expect. X's high output is fed into Y's input, so Y output is low. There are no conflicts. Each inverter is feeding the other with a signal that is compatible with the status quo. The system is stable, because both inverters are continuously confirming and reinforcing each other's current condition.

Circuit 3 is similarly stable, but the roles are reversed. It is inverter X than must output a low signal, and Y's output is high. It should be clear that this circuit is able to adopt and maintain one of two stable conditions. We call such a circuit "bistable", for that reason.

The problem here is that we have no way of changing from one state to the other, except via brute force. In circuit 2, where Y outputs low, imagine that we can somehow overcome the very strong output signal from Y, and impose our own voltage instead. We could short circuit the output to +5V, forcing that output high against the gate's will. That's not recommended, of course, because one should never short circuit a gate's output to any low impedance source. However, we do just that, we connect Y's output to +5V, a logical high.

Imagine what would happen. I force the output of gate Y high. Immediately, gate X sees its input go high, and it changes its own output accordingly, to low. Suddenly gate Y also sees a change in its input to low, and changes its own output to high, as an inverter should do.

This new high output is no longer fighting the short circuit to +5V that we imposed, and the whole system has entered a new stable condition. I can remove the short circuit, and it will maintain this new state - which is exactly the state of circuit 3. The change we imposed has propagated around the loop, to conform with the condition we imposed, and it will maintain this new state even after we remove the initial purturbation that began the whole state "flip".

Now that we have a state of affairs that is represented by circuit 3. We can return to the state of circuit 2 simply by imposing our will. If we want the output of gate X to become high again, there are two ways to achieve this; either momentarily connect that output to high, or connect the other output to low. Both actions will have the same result, to cause the change to propagate around the loop, until both gates conform to the new condition. State will "flop" back to the conditions in circuit 2.

Now it should be clear why we also call these systems "flip-flops".

The most important thing to take away from all this is that the signal we used to flip or flop state is ephemeral. It was a brief, temporary imposition of a forced high or low to either side. The new state will be maintained even after the initial cause of the change is removed. In this way the bistable flip-flop behaves as a kind of memory. It only changes state when asked to, and it maintains that state long after the request was made and forgotten.

The state is said to be "latched", the word "latch" also being used to describe a circuit that maintains state in this way, that has "memory".

Take a look at the truth table for a two-input NOR gate:

      enter image description here

In particular, examine the rows in the red box. Notice that if input A is held low, then output F is simply the inverse of input B. In other words, the NOR gate is an inverter if you keep one of it's inputs low. This means we can use NOR gates to implement the same latch configuration:

schematic

simulate this circuit

Again, those two circuits are identical. The one on the left is the more common representation, since it complies with the convention signals travel left to right, with inputs on the left and outputs on the right.

The circuit behaves exactly as the version with inverters did, because the "unused" inputs are connected to ground, 0V, low, logic 0, and these NOR gates are just fancy inverters.

Now look at the truth table, the last two lines. Can you see what will happen if we bring input A high? In fact what would happen if we bring either input high? Any high input will force the gate's output low, that's the job of a NOR gate.

Suddenly, we have a way of gently persuading a gate to bring its output low, instead of using brute force, instead of risking damage to the gate by short circuiting its output to a power supply rail.

So if gate X output is currently high (and Y is low, therefore), all we have to do to "flip" states is bring gate X's other, unused input high. All the propagation of state change will happen as it did with the inverters, but from a civilised, gentle, momentary high pulse.

Similarly, with gate Y now having a high output, we can "flop" states back again by bringing gate Y's other input high, just momentarily.

Naturally then, we don't connect the "unused" inputs to ground, we use them as proper inputs, and call them "set" (S) and "reset" (R), for reasons which I hope are clear now. And we call the whole thing an "SR flip flop", or "set/reset latch":

schematic

simulate this circuit

Here are some waveforms that you can expect from this circuit:

enter image description here enter image description here enter image description here

The top plot is the SET input signal, then RESET, and the bottom plot is output Q. The main features to note here are:

  • A momentary high SET pulse causes Q to go high, and this state is maintained even after the pulse is finished.

  • A momentary high RESET pulse causes Q to go low, and this state is maintained even after the pulse is finished.

  • If Q is already high, then SET pulses cause no change.

  • If Q is already low, then RESET pulses cause no change.

\$\endgroup\$
2
\$\begingroup\$

A latch acts as a memory, it is neatly explaind in this truth table:

enter image description here

Source of this picture.

Note that there are two lines describing the situation where the inputs S = 0 and R = 0.

Which one applies depends on what happened before S = 0, R = 0.

If we had: S = 1, R = 0 and then: S = 0, R = 0: we get Q = 1, Q'= 0

But if we had: S = 0, R = 1 and then: S = 0, R = 0: we get Q = 0, Q'= 1

The other lines are not dependent on the history so they work like normal combinatoric logic (a certain input always gives the same output).

\$\endgroup\$
3
  • \$\begingroup\$ Thank you for your answer. But, I still do have confusion. As you pointed, A certain input always gives the same output. Do you mean For S= 1, R = 0 it will always give Q = 1 & Q' = 0 and vice versa? But for S = 0 & R = 0 state, output will always depend on what was before. That is S = 0 & R = 0 is memory state. Another question was like, for S= 1 & R = 0 it does not depend on what was before. But you said they work like normal combinatorics. I didn't get this point. \$\endgroup\$
    – F.C. Akhi
    Commented Oct 22, 2021 at 8:12
  • \$\begingroup\$ But you said they work like normal combinatorics. Make the truth table of a single NOR gate. Now do the same for the Latch but only for all input combinations of R and S but skip R = 0, S = 0. For those 3 combinations of R and S you can always detemined what the output will be, the history does not matter. That behavior is called "combinatoric logic". \$\endgroup\$ Commented Oct 22, 2021 at 8:37
  • 1
    \$\begingroup\$ @f_chowdhury Yes S=0&R=0 is memory state. That is the whole point of this circuit. The reason why people use this circuit is because they want memory. \$\endgroup\$ Commented Oct 22, 2021 at 9:03
0
\$\begingroup\$

For helping understanding "how RS latch" works, I have tried making an "interactive" k-map ... (a bit "difficult" with simulator).

Same delays for the two NOR gates.

See also https://www.ee.ucl.ac.uk/~ademosth/E757/Topic6.pdf

Outputs are named in general : Q1 and Q2 !!!

My k-map :

enter image description here

I used microcap v12
(K-map is not displayed, only the state where you are, see example). How to insert too long text file circuit, or link ?

enter image description here

Starting with one (R,S)=(0,1) configuration, (_q1,_q2)=(0,0). start case 1, go to case 9, see transient window. enter image description here

Going to (R,S) = (0,0) -> case 9. Direct jump. No transient case.

enter image description here

Now, manipulating R, going to (R,S)=(1,0) -> from 8 to transient cases A, 2, finally 6.

enter image description here

You can even show the "oscillation" of this RS-latch ...

Only in "Transient window", because between "instables" cases and transitions.

Nota : if the delays are not the same, it is not the same behavior !!!

Starting from (R,S)=(0,0) ... Oscillating between 0 and C cases.

enter image description here

If _q1 is faster then _q2 ... this occurs ... (_q1,_q2)=(0,0) then (_q1,_q2)=(1,0).

enter image description here

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.