We are looking at implementing an architecture that makes use of eXecute In Place (XIP) over QSPI in order to overcome storage constraints; our firmware has grown too large to live in the on-chip storage.

There is some belief that being able to use XIP is dependent on the flash chip itself but I can't find anything that suggests this. Rather, it seems like something thats implemented on the micro and can only be helped along by the flash.

Our flash chip supports QSPI and the Fast Quad Read I/O setting.

Does anyone have any experience with this or can point me in the right direction?

To be specific about what we're wanting to use:

Micro - Renesas R7FA6M2AF3

Flash - Winbond W25Q32JVZPIQ

  • \$\begingroup\$ Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. \$\endgroup\$
    – Community Bot
    Oct 22 at 15:27

XIP is not a feature of the flash, the MCU just does reads to flash to fetch code into cache for execution, but of course the flash needs to use the same protocol what the MCU wants to use when using XIP.

If the QSPI protocol matches what the MCU expects to implement XIP and the flash is fast enough so it won't be a bottleneck then it should work.

  • \$\begingroup\$ If you have experience with it, do you know if XiP is performant enough to be used instead of on-chip flash? My instinct is to use the PLL to boost the clock frequency for the QSPI bus to get something akin to operating like an on-chip flash but I'm not much of a hardware guy. \$\endgroup\$ Oct 22 at 15:31
  • \$\begingroup\$ No, but any serious MCU manufacturer would have documentation how it performs. \$\endgroup\$
    – Justme
    Oct 22 at 15:55

XIP is based on a cache memory that coherently fetches in advance a certain number of instructions from the external flash memory and then presents them to the CPU for execution.

There's also look-ahead hardware predictor that empties the cache memory whenever the assembly program contains a jump to an address that is not contained in the cache.

Each time the cache gets emptied the CPU stalls for a certain number of clock cycles.

Some expansive microcontrollers have 2 QSPI interfaces that can read 2 flash chips simultaneously. That doubles the execution speed of the program.


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