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I have done a Verilog module for clock and data recovery (CDR) using DLL ( this is for simulation purposes only) I used Modelsim for simulation. In the transmitter (Tx), I only have a (clock that has a random phase shift) and random data both going to an XOR gate. The output is just data out. I also used Manchester coding scheme as a data format. The receiver (Rx) doesn't have a clock, it has to extract the clock and data using DLL. I would like to know what tools would help me to measure the phase shift (or jitter in the time domain)? I believe Simulink Matlab can do this but how to utilize my Verilog code? Is there any other software that is good in academia?

I want to see which coding schemes (including Manchester, NRZ, RZ) that is more sensitive to jitter? I read that DLL is better in tolerating jitter than PLL and it doesn’t need a clock like in the case of PLL it has VCO. Having many chips communicating with the same clock will make issues in sync so getting rid of the clock in each chip and using DLL with the help of self-timed Manchester coding might solve this issue but again back to the jitter how we would calculate the BER, jitter and other parameters, maybe eye diagrams, that are related and how we model the timing uncertainty?

Kind Regards

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  • \$\begingroup\$ Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. \$\endgroup\$
    – Community Bot
    Commented Oct 23, 2021 at 7:33

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Perhaps you can define what BER you expect and what SNR you have to deal with. The type of noise matters in correlating the two and will determine if you can't improve the SNR then this dictates what method of clock recovery is best.

The reason is DLL is fast and quick but clock jitter equals data jitter so the jitter between clock and data is equivalent to the sum of data+ clock jitter / data bit interval. This jitter could due to Gaussian Noise, Inter-Symbol Interference (ISI) from unequal filter group delay, impulse noise, power supply noise, RF interference or any other source of jitter.

Actually a signal BW matched PLL SERDES clock recovery with coherent integrate and dump detection is the best.

But a Delay Locked Loop (DLL) clock recovery is the simplest using 3/4T for the one-shot period triggered from the correct polarity edge of the clock signal.

After you define your signal and noise property specs, then we can get started.

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  • \$\begingroup\$ Jitter will cause an error accumulation in clock jitter. As I said previously using DLL was just to get started with CDR and because I don't want to use a clock if we talk about chip to chip communications that have the same clk. This will lead to a sync issue. If we use PLL we would have an oscillator+the DLL is better in dealing with jitter than PLL. The noise (or in other words the jitter in the time domain), is just a random phase shift in the Tx clk which will lead to some consequences drift in the delay lines which lead to not having a match with the clock out and one of the delay lines! \$\endgroup\$
    – Hammam
    Commented Oct 24, 2021 at 12:28
  • \$\begingroup\$ That is not my experience. @Hammam The PLL filter characteristics may either amplify or attenuate noise.... in-band noise like ISI is rejected unlike DLL that reduces data shift margin then again with clock shift, then clock then data in opposite alternating jitter directions. The worst case ISI pattern was usually 011011 or 100100 or 6DBh But then using Raised Cosine filter fixed all ISI noise introduced by filters then it was channel group delay distortion and impulse noise \$\endgroup\$ Commented Oct 24, 2021 at 14:11

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