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I had the assumption that resonant mode switching converters operate at the exact resonance frequency of the LLC tank and other parasitic elements inside the transformer, but as far as the controller ICs go (like CM6901 for example, or ICE2HS01G,) I see them using frequency modulation for regulating output voltage. That means the converter is actually operating in a region around the resonance frequency and not the exact resonance, and using the offset frequency to lower the power output

Isn't it better to operate at the resonant frequency, with PWM to regulate the output?

Why don't the controllers have a kind of feedback from transformer to detect the resonance frequency themselves? Like a zero crossing detector on current in the primary to lock the phase onto as the current will follow a sinusoidal wave from after each switching cycle because of the capacitive coupling in the LLC tank.

I think quasi-resonant converters work the same way but in full-bridge high power converters I don't see that feedback.

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  • \$\begingroup\$ the main reason for resonant converters is that you avoid switching like with pwm that creates EMI. Yes, the converter adjusts the frequency around resonance in order to regulate - this is the benefit of the technique. \$\endgroup\$
    – Kartman
    Commented Oct 24, 2021 at 0:43
  • \$\begingroup\$ Imagine the settling times for that. \$\endgroup\$ Commented Oct 25, 2021 at 7:21

2 Answers 2

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The classical control method for driving a series resonant converter such as the LLC consists of controlling the switching frequency directly from the error voltage. This is called direct frequency control (DFC) and you accomplish this function by using a voltage-controlled oscillator (VCO). A LLC is made of a series inductance \$L_s\$, a series capacitor \$C_s\$ and the magnetizing inductance \$L_m\$ of the isolation transformer:

enter image description here

If you plot the transfer function of a LLC at different load conditions, you will clearly see two resonant frequency: one in heavy-load conditions where the magnetizing inductance \$L_m\$ is shunted by the reflected load and another one in which both the series inductance \$L_s\$ and \$L_m\$ resonate with the series capacitor. The below picture reproduces a typical gain graph for a LLC:

enter image description here

In this picture, you can distinguish two slopes: one, positive, where the voltage increases as the frequency also goes up, this is the so-called capacitive mode and a second slope, negative, in which the output voltage decreases as the frequency increases. This second part is call the inductive mode and both terms, cap. and inductive modes, relate to the impedance offered to the half-bridge while driving the LLC network with a sinusoidal signal.

The inductive mode, which is above the resonant frequency, is the one where you want to operate the LLC. It provides zero-voltage switching (ZVS) to the half-bridge MOSFETs and zero-current switching (ZCS) to the secondary-side rectifiers. If you accidentally go to capacitive mode, you not only lose the previous benefits but also reverse the control law with all deleterious consequences. Recent controllers now include a so-called capacitive mode detection which makes sure the upper- or lower-side MOSFETs are turned on when the voltage across drain-source is zero volt meaning the body diode conducts. This is done by observing the half-bridge node.

For best efficiency, most designers design their LLC for operating at the resonant frequency in full load. However, operating conditions such as input voltage changes and load values imply an operating frequency not exactly at resonance but close to it. You can also deliberately adopt a different strategy where, depending on the ratio \$\frac{L_m}{L_s}\$, you lose regulation in light load and purposely increase frequency until skip cycle is entered. It was the adopted control strategy for former LLC controllers where no-load standby power was important.

Now, I spoke about DFC but recently-released controllers now adopt different control schemes where frequency is indirectly controlled like with charge control techniques such as the one described here. This drastically changes the control-to-output transfer function to a simpler ac response and eases loop design.

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  • \$\begingroup\$ The reference link appears dead; I don't see a handy (free) replacement, but the author's thesis seems to have relevant information in it: qspace.library.queensu.ca/bitstream/handle/1974/12346/… (Ch6, p.104 (124) onward). For another reference, if I'm not mistaken, this is (or looks very similar to, anyway) what TI calls "hybrid hysteretic control", e.g. UCC25640x family controllers. \$\endgroup\$ Commented Aug 30, 2023 at 14:06
  • \$\begingroup\$ @TimWilliams, thank you for pointing this out, I did update the link with the IEEE URL. Yes, the TI part looks very similar even if they claim it is truly different : ) One issue I spotted with some of these controllers is the difficulty to keep an exact 50% duty ratio during transients. I made a model that I described in my seminar on LLC control methods. \$\endgroup\$ Commented Aug 30, 2023 at 15:48
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Verbal Kint's answer covers pretty much everything, but I thought it worthwhile to wrap up this loose end:

Isn't it better to operate at the resonant frequency, with PWM to regulate the output?

This can be done, but care is needed.

Background

Note that, for typical output networks, we can use a steady-state sinusoidal approximation, i.e. ignoring the harmonics of the inverter's square-wave output. This is justified because the network is largely inductive at harmonic frequencies, so the harmonics go as 1/N in voltage, and 1/N2 in current (a somewhat triangular ripple waveform), and together amount to <10% of inverter output (apparent power), a fairly small error.

In short, we can model the resonant network as an RLC circuit at the fundamental frequency, and ignore the effect of harmonics entirely.

To ensure ZVS, we require an inductive load. That is, at the instant of turn-off, some inverter current persists, pushing switch node voltage (i.e., flowing into the switch capacitances) fully to the opposite supply rail (commutation), at which point the opposing transistor can turn on at a leisurely pace (i.e., delayed by some "dead time", and give or take gate resistance if any), before load current reverses and it must be turned on to continue repeating the cycle.

Why care is needed

That necessary inductive current can only circulate if the inverter maintains a low output impedance (CV characteristic). If the inverter should go open-circuit, then the reactive current would discharge as a flyback pulse and subsequent ringdown; the node voltage becomes much harder to follow, then (the ringing might be at some MHz, and give or take propagation delay through the controller and driver, it might not be able to turn on coincident with the respective valley point -- if it were designed to handle operation in this regime at all).

Now, we're generally working with bridge circuits, so the output is never fully high-impedance, and flyback is constrained to at most the supply voltage -- but this is only true while the (unclamped) flyback amplitude would exceed the supply voltage. If reactive current were very low, it might be that the switch node voltage only commutates partway, resulting in the opposite side transistor turning on into a large voltage drop (and producing a sudden transient in the switching loop) -- increasing emissions and switching loss.

And so, if we consider the half-bridge inverter, with variable duty cycle gate drive (in the normal balanced modulation ala TL494 and friends), we find a problem: as we decrease PWM%, at first, nothing happens (reactive current holds the voltage against the rail); eventually, conduction angle drops below the load phase angle* and inverter voltage "lifts off" the rail just before the opposite transistor finally turns on. For even lower PWM%, it might fully rebound (to the opposite side), or bounce back (nearly all the way) again; etc.

*Not exactly that comparison, but reverse conduction angle is a function of load phase angle.

In short, the control law is extremely nonlinear: at high PWM%, nothing happens (well, efficiency drops slightly as synchronous rectification is lost); at medium PWM%, losses increase dramatically while power output decreases only modestly; and at low PWM%, power output decreases non-monotonically as the voltage rings down between pulses.

What can we do about it?

The key observation is that the half-bridge goes open-circuit (an undesirable condition) when neither switch is activated, and we have no further degrees of freedom (only one or the other switch can be on, or neither; both would cause an explosion :) ). Using MOSFETs with body diodes (or IGBTs with co-pack diodes, etc.), we get an extra switch "for free" during the dead time, when some inductive current is present -- hence the flexible dead-time period. But beyond that, we need to employ additional circuitry to enforce the low-Z condition that our system (the resonant network) requires.

The half-bridge can be adapted into the three-level inverter, where a bipolar supply is used, and an additional (bidirectional) leg shorts the network to the supply midpoint, inbetween the +/- pulses.

The full bridge can be used directly, where instead of pulsing opposite corners (i.e. the basic half-bridge case paired with its inversion), we drive both sides with full square waves, phase-shifting one leg relative to the other -- phase-shift pulse width modulation (PSPWM). This way, the inverter's output is always 100% driven (fully defined) and thus low impedance, but the voltage difference between legs (i.e., where the output network is wired, what it sees) is a bipolar pulse wave with variable duty cycle.

(Note that we get an identical waveform from the half-bridge forward converter in CCM; but in that case, the output is held low due to output inductor current circulating through the rectifier.)

In any case, having a continuous low-Z inverter output, allows the fundamental component to vary nearly proportionally, and thus a reasonable control law is obtained.

The major downsides to these are, the greatly increased complexity of a three-leg inverter (a bootstrap gate driver can be used with the added leg, at least), or the greatly increased EMI of a full bridge PSPWM scheme (notice the network/transformer sees a common-mode waveform of 100% full inverter switching edges!). The PSPWM also drives the inverter itself at full wave regardless of load condition; adequate load current must still flow to ensure ZVS, restricting the load area (i.e. permissible range of Z = R + jX of the output network) at low duty cycle, or else incurring hard switching loss/EMI. There are also fewer controllers available for PSPWM, or, additional logic is required to drive a three-leg inverter.

Regardless, note that we would still drive the inverter slightly above resonance, to maintain ZVS; a phase-locked loop might be used to implement this. (Which has the downside that phase error is proportional to output level, but this isn't a concern for fixed-output supplies; it's more of a concern for wide-range variable supplies, or induction heating.)

In comparison, the main downside of frequency modulation is, the compensation (time constant) varies as the difference between driven and resonant frequencies. For typical LLC networks, the Q factor is very low (less than 1), so the peaking is nonexistent and response is nearly 1st-order, making this a quite comfortable solution. (Dynamics are further improved in charge-compensated methods.)

For high-Q applications, like wireless power transfer or induction heating, the peaking can be quite severe, either forcing extremely slow (worst case) compensation, or some kind of custom dependent-parameter (non-LTI, adaptive/self-calibrating, or nonlinear) controller.

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