I was a bit surprised to find this question and its answer.
simulate this circuit – Schematic created using CircuitLab
When daisy chaining several HC595 or HC594 shift registers, with shared SCLK (serial input clock) and RCLK (output register clock), can there indeed be a timing violation that leads to wrong data being clocked into SDI of the 'later' chips (SR 2 on the right side of the schematic)?
The answer in the link above implies that - upon receiving an SCLK edge - an SDI data could be sampled after the SDO data from the previous register has updated. I have never paid attention to this because I thought that by design the propagation delay will make this impossible. My understanding was that the CLK would always arrive first and the SDO update would be delayed by the propagation delay from CLK to SDO inside the preceding chip in the chain.
Examples:
Generic 74HC parts seem to confirm that the minimum required SDI hold time is usually <3 ns, whereas the minimum CLK-to-SDO propagation delay is at least 12 ns.
The faster LVC series is not quite so clear in this regard (example from Nexperia): the minimum propagation delay is 1.5 ns only, but the typical hold time requirement is around 0.1 ns with the absolute worst case value given to be the same as the CLK-to-SDO propagation delay values. This suggests to me, that even the LVC is designed such that SDO can never overtake the CLK in a daisy chain.
Have I been careless/lucky? If so, under which conditions can these violations appear and how to fix them assuming I want still want to use a highish SCLK of ~20 MHz?