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Typically an N-MOSFET is used for low-side switching and P-type for high side switching. That's why transmission gates use both an N and a P-type MOSFET.

But I don't understand how a P-type for low-side and an N-type for high-side switching would create a degraded output. It would be nice if someone could explain this to me briefly.

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    \$\begingroup\$ That way, the gate drive voltages are usually within the supply rails ... except for weird cases where the supply rails are 3V or less, with FETs requiring 5 or 10V gate drive. \$\endgroup\$ Oct 25, 2021 at 20:02

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Typically N-MOSFET is used for low side switching and P-Type for high side switching. That's why transmission gates use both N and P-type MOSFET.

Actually, NMOS is also often used for high-side switching in cases of higher supply voltage which would require extra gate-drive circuitry for a PMOS anyways since pulling the PMOS gate all the way to ground would exceed its maximum tolerable Vgs. If you need extra gate-drive circuitry anyways, you might as well just use a cheaper, more efficient, more available NMOS on the high-side which also requires gate drive circuitry.

But I can't correctly understand how a P-Type for the low side and N-Type for high side switching creates degraded output. It would be nice if someone could explain this to me briefly.

What you are looking at there is called a "source follower". More specifically, a PMOS source follower and an NMOS source follower stacked on top of each other.

It's not really acting as a switch. It's a source-follower being pressed into service as a switch. So it's not very efficient and not for high power. But that configuration is chosen when only low power is involved and you do not want extra circuitry to deal with shoot-through since the source-follower inherently cannot shoot-through when both high and low-side MOSFETs gates are tied together and driven from a common signal. You also find it amplifier outputs which should give you a better impression of what it really is since it can drive signals at partial levels between on and off.

You can look up what a source follower is but here is a summary of what is relevant:

Remember, Vgs controls how much the MOSFET conducts. Vgs, the voltage between the gate AND source terminal. Not Vg (gate voltage referenced to ground). In a source follower, the source terminal is not connected to ground, but the gate is being driven by a voltage referenced to ground. As the MOSFET conducts more and more the voltage drop across the load causes Vs (source terminal voltage referenced to ground) to change. Since Vg is being driven relative to ground, this changing Vs moves towards Vg which reduces Vgs thereby preventing the MOSFET from completely conducting. An equilibrium is reached between full off and full on.

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For an N-type to switch on, the gate-source voltage has to be at least above the Vgs threshold, and preferably even more than that. Otherwise, the n-FET will not be fully turned on and thus will shed significant power.

Example: high-side connected n-FET with gate-source (Vgs) threshold of +2.5V, Vin +10V on the drain, source to load, gate also at Vin = +10V. What will the output be? Answer: +10V - (Vgs threshold) = +7.5V. So the output will go no higher than 7.5V. This means a voltage drop of 2.5V in the FET, which will be shed as heat.

So we need a gate voltage of at least 10V + Vgs threshold, or 12.5V, to get the job done. We'd really like the gate voltage to be more like 15 to 20V to drive the FET fully into saturation (lowest possible Rds(on)) for best efficiency. How to do that? Many DC-DC buck regulators use that high-side n-FET configuration and use a bootstrap circuit to create the higher-than-Vin voltage for the gate drive. This ensures the FET is turned on fully and has the smallest possible voltage drop.

More about bootstrapping here: https://techweb.rohm.com/knowledge/dcdc/dcdc_sr/dcdc_sr01/829

Why bother with bootstrapping if one can just use a p-FET instead? It’s worth the extra trouble to do the bootstrap with the n-FET because n-FETs typically have better on-state characteristics than p-FETs and thus will be more efficient.

On the other hand, a p-FET needs the gate drive to be below the drain and source by at least the Vgs threshold to fully turn it on. The difficulty with using a p-FET on the low side is making a gate drive that’s at least one -Vgs below the ground reference. It’s not impossible, but it’s more trouble than it’s worth compared to just using an n-FET.

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