I'm designing a wearable device that needs charging capabilities and to convert the 3.7 voltage of the battery to 5 volts to power the MCU.

I'm using the MCP73871 charging chip and TPS61090RSAR booster chip in combination which is in essence just the replication of the Adafruit PowerBoost 1000c. Using the schematic provided by Adafruit I was able to replicate the schematic to incorporate with my overall wearable schematic and pcb design.

From what I can tell everything should be working correctly but once the board was milled and the components soldered, no output is seen on pin 20 and 1 of the MCP chip.

Below I'll include the section of the schematic and PCB in question. My fear is the design of the PCB or schematic is incorrect but I could also see that I just don't know how to solder SMD chips and that is the issue. I'll also include an image of the soldered components on the PCB.

I used a heat gun to solder the chips and other components. That could be an issue but I wouldn't know how to check. I've checked for shorts and everything seems to be working correctly.

Note that in the image of the PCB I don't have the TPS chip soldered and an inductor. I did this to test if this was causing an issue but I've tested with and without the TPS chip with no success.

Any advice will be greatly appreciated since this is really bringing my confidence down in creating electronics.


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PCB Model

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PCB & Components

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1 Answer 1


The PCB layout you show is exactly how power regulator circuits must not be done. It has to be taken as a lesson learned, and re-done. The board you got will not work reliably, and even if you could patch it up to do so, it'll still perform very poorly in terms of electromagnetic compatibility (EMC) and is likely to interfere with nearby RF circuits.

in essence just the replication of the Adafruit PowerBoost 1000c

When it comes to high-bandwidth circuits such as switching regulators and LDO regulators, the schematic and layout go hand in hand. If you claim that you replicate a circuit, you must replicate the layout as well. At the frequencies involved here, a poor layout changes the schematic. It does so by introducing:

  1. Parasitic impedances, mostly inductive, within the low impedance circuits.

  2. Parasitic transformers between low- and high-impedance circuits.

The circuit you have laid out adds those parasitic components everywhere they should not be, pretty much, and thus the claim of replicating anything goes out the window. It certainly was your intent, of course, so let's see what we could do to improve things.

In order to claim that you replicate the schematic, you must ensure that you didn't add those parasitics everywhere. And that's where the layout comes in - it is critical in ensuring that your physical circuit matches the intent of the schematic diagram.

You have extremely long thin traces within the switching loops, and within AC current loops that are critical for stabilization of the regulator. Remember that voltage regulators - be they switching or linear - are feedback systems, and everything you have learned in theory of such systems applies. Even if you didn't take a formal course, the nature still does things the same way, so you will learn some basics as you develop the intuition about what works and what doesn't. Thin traces are parasitic inductors and resistors. Long traces form antennas that radiate and receive, and they also form transformer windings that mutually couple.

The ground planes on top layer of your layout are not really connected to anything at high frequencies - a couple vias far away doesn't count for much.

Regulator circuit layouts must be very compact in the high current paths and in high impedance paths.

  1. See if there is an evaluation board for the switcher. If so, the documentation for the board will have all PCB layers so that you can see how to do the layout reasonably.

  2. If no eval board is available, look at the datasheet of the regulator. It does include a layout example. Use it!

For a general idea of how such layout might look, below is my own example. All three chips in the picture are regulators. The two on the top are switchers. The one on the bottom is linear. Note how the switching- and transient-carrying current loops are laid out as large copper pours ("polygons"), instead of thin traces.

a photograph of a power supply section of a PC board

This image is almost exactly an inch across (0.97")

The idea is that the critical AC high current loops should be small. Those are marked up on the picture below, in dark red. For switchers, those loops carry the wideband switching waveform. Even though the switching frequency is "only" 1MHz, there is plenty of energy out to 20MHz or so. It is imperative to:

  1. Minimize the loop area of low impedance (power) circuits, for it acts as an antenna and radiates out the switching energy.

  2. Minimize the loop impedance in those, for it not only keeps the regulator stable, but also decreases voltage spikes and semiconductor stress, and improves transient response.

  3. Minimize the loop area of high impedance (feedback/control) circuits, for they are very sensitive to inducted interfering voltages from adjacent high current loops. Each high current loop is a transformer winding that does its darndest to couple to high impedance loops nearby - your job is to thwart that.

For the linear regulator, the short AC current loop decreases the input and output AC impedance, and thus stabilizes the regulator and improves both load regulation and line rejection.

a power supply section of a PC board, with critical AC current paths indicated

Before laying out your own design, you must identify all high current "power" loops, and then design to minimize their area and impedance; and identify low current high impedance "sensitive" loops and keep their area small as well.

Current flows in closed circuits, thus you must always identify circuits as closed loops - they must begin and end at the same point, and follow paths of similar impedance within the chip itself. For low impedance loops, that means they cross power elements on the chip - switching transistors, pass elements, and switching diodes. For high impedance loops, they go through the feedback circuits or digital input circuits.

In the specific case of your circuit, the critical paths that must have small area and low impedance are:

  1. U3:VBAT, through C1, through C2 to U3:OUT, closing through the internal pass element.

  2. U1:SW, through the inductor, through C3 to U1:PGND, closing through low-side switch.

  3. U1:SW, through the inductor, through C3, through VOUT decoupling C5||C14, to U1:VOUT, closing through high-side switch.

The high impedance loops are in the feedback circuits that include the U1:FB.

You can see the twin loops in U1 if you superimpose the circuit on top of the functional diagram from the datasheet. The loops are indicated with dark blue and green colors below:

functional diagram of the switching regulator with important circuit loops superimposed

And below are the same loops, but superimposed on the layout example from the datasheet, with their area shaded: the goal is to keep those shaded areas as small as practical:

example layout of the switching regulator with important circuit loops superimposed

This layout is supposed to be about 1/2" wide!

There are three design details that are purposeful, but their presence may not be immediately obvious.

  1. In the light blue pair of feedback loops, if given a uniform external varying magnetic field, the voltage induced into FB from the left loop is exactly the opposite of the voltage induced from the right loop! Thus, this layout almost completely neutralizes the coupling from low-gradient external fields. The farther you get from the interfering loop, the lower the gradient, and thus these two little loops are expected to do a good job of rejecting the interfering fields generated by the relatively far away purple and green loops.

  2. Similar compensating arrangement of two blue loops is used to establish the low battery cut-off voltage. The loops have approximately the same area but have opposite influence on the LBI input in uniform external field, and thus largely cancel induced voltages. This prevents spurious triggering of the low battery cut-out circuit, and also minimizes the amplitude of induced interfering voltages, minimizing the likelihood of a transient that would trigger overvoltage protection on that input pin.

  3. Now look at the green loop: it is "twisted in the middle" like if you had an oval and twisted it into figure-8. Since it's one circuit, the circuit flowing in both half-loops is the same, but it's flowing in opposite directions. If the current flows clockwise in the upper half-loop, it is flowing counter-clockwise in the bottom loop. The green loop's layout thus neutralizes about 30-40% of its far field compared to a non-twisted layout. In all likelihood, this is not accidental, but a conscious design decision: the layout of the semiconductor chip itself, and its packaging, allow this to happen.

If anything, this chip's packaging design and the layout it facilitates are a tour-de-force of good engineering.

In all likelihood, there'll be decent examples available for the U3 in your circuit as well :)

  • \$\begingroup\$ Thank you for the detailed response. So in the case of the MCP chip, is the output the source of the switching and would need a large pour to minimize the loop? I majored in CE so electrical systems are not my strong suit for sorry for any dumb questions. \$\endgroup\$ Commented Oct 26, 2021 at 16:25
  • 1
    \$\begingroup\$ @RickyHernandez You must understand the reason behind every layout decision you make. Look at the layout example in the datasheet. Then identify the current loops, so that you can see how their area and impedance were minimized. Then see how sensitive high impedance feedback circuit has its two loops kept small. It's not only about pours, but also about keeping things as close together as feasible. \$\endgroup\$ Commented Oct 26, 2021 at 16:41
  • \$\begingroup\$ Wow thanks again for such the extensive response. I think I understand that the layout needs to be more densely packed and traces need to be expanded for the current loops so the area and impedance can be reduced. \$\endgroup\$ Commented Oct 26, 2021 at 17:07
  • \$\begingroup\$ quick question, will this be possible if only two layers are being used? I'm having this milled at my university and only have access to two layers here \$\endgroup\$ Commented Oct 27, 2021 at 20:34

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