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The picture shows 0805 LEDs and one last 0805 resistor connected to the GND pour.
What you are asking for is the 'component footyard' which is defined in IPC7351B (soon to be updated… for something like 5 years)
As already answered at the end it boils down to your fabrication capabilities however there are general guidelines for the most common situations. If you are doing class 1, producibility level B (general electronics with normal production yields) as a rule of thumb (for SMD components) you enclose all your copper pads and your body (in the maximum material position i.e. bigger as possible under package tolerances) and add 0.25mm of courtyard all around.
The general idea is that you then place the components so that the courtyards do not overlap (some EDA can check this).
This is a very generalized idea, the standard is actually full of tables with all the numbers (for example for BGA it's recommended to add 2mm all around for reworking). Also the standard is very old and many are using the unpublished C revision, but it's a start (unless you are designing, say, a smartwatch).
In general pick and place capabilities are about 0.1mm and layer to mask registration is about 0.2mm, there is a complete statistical analysis in the standard if you want the full story.
As for the pad join: there is no issue on routing them directly, or even entering thru the diagonal, expecially if the pad is squareish. With thin long pads like for SOPs it's slightly better to enter from the thin side but only to avoid delamination if you need to rework.
Spacing depends on your board fabricator, the pick-and-place technology and your ability to properly label the locations on the silk screen layer (if required by the company that populates the board).
There is no exact answer to such a question.
