# Rise time vs Slew Rate

I am using this device which is a LS1046. It list slew rate as 1V/ns to 4V/ns. It is measured over a region of .35XOVDD to .65XOVDD where OVDD is 1.8V So over the range of .63V to 1.17V which is .54V

So the rise time for 1V/ns is .54/1 = .54ns and for 4V/ns is .54/4 = .135ns

So range of rise time must be between .135ns and .54ns. Did I calculate this correctly?

(a) Yes, you are correct but you have only described that partial range.

A further description would be for the full 1.8 V SYSCLK driver circuit. You'll need that to specify that circuit, be it a clock oscillator module, from a logic pin or a bespoke oscillator circuit.

The measured range is (0.35 x OVDD) to (0.65 x OVDD), which for the record is a range of (0.3 x OVDD).

The required 1.8 V clock rise time at 1 V/ns is 1.8/1 = 1.8 ns.

The required 1.8 V clock rise time at 4 V/ns is 1.8/4 = 0.45 ns.

That takes the driver output to be perfect, switching between 0 V and 1.8 V. That will give us the worst case transition times, though, which is a good starting point. The best case would be switching between the specified 0.4 V to 1.35 V for a Vmax_low and Vmin_high, a voltage swing of only 0.935 V.

(b) Relating this back to the SYSCLK period...

The IC specifies only a typical frequency of 100 MHz, so a 10 ns period.

Your rise/fall times can be 0.9 to 3.6 ns, making the edges 9..36% of the period. The faster the edges, the less jitter in the IC's internal SYSCLK frequency because the imprecise logic transition points (and any uncertainty range) are passed through more quickly.

So you would design for the fastest SYSCLK rise/fall times you could but there is no benefit in going faster than 0.45 ns because that is specified as sufficient to maintain the IC's performance.

• why are you using the entire 1.8V range for this? Shouldn't it be where they measured the slew rate (ie .35OVDD to .65OVDD)? Commented Oct 28, 2021 at 10:37
• @Matty, see paragraph 1 of my answer. Your question doesn't explain anything about the circuitry around this, which it should. A push-pull driver for this input will have rise and fall times specified for the full range, not part of it. Hence the confirmation of your maths plus this data. Commented Oct 28, 2021 at 11:47
• so the driver has a rise/fall time of 2.5ns at 20% to 80%, the Voh = 90% of VDD and Vol = 10% of Vdd. For Vdd = 1.8, Voh = 1.62 and Vol=.18. So 20% of that is .288V and 80% of that is 1.15V. So 1.15-.288 =.862V over 2.5ns which comes out to .344V/ns which looks too slow for the input clock. Does this make sense? Commented Oct 28, 2021 at 14:54