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Consider the following device; a ripple counter:
module ripple(out2, out1, out0, clk);
input clk;
output reg out2 = 1'b0, out1 = 1'b0, out0 = 1'b0;
always @ (posedge clk) begin
out0 = out0 + 1'b1;
end
always @ (negedge out0) begin
out1 = out1 + 1'b1;
end
always @ (negedge out1) begin
out2 = out2 + 1'b1;
end
endmodule
Is such a construct generally synthesizable? What determines which connections may be used as clocks?
It may be synthesizable but not generally implementable. Tools that layout a synthesized netlist have to meet timing constraints for setup and hold from output of one register to the input of another. If you make too many ripples, it becomes too difficult to use your outputs if they need to feed into logic with another clock.
Regarding the question about reset, here is a slightly modified code, with a reset input instead of "initialization":
module ripple(
input clk, rst,
output reg out2, out1, out0
);
always @ (posedge clk, posedge rst) begin
if (rst)
out0 <= 1'b0;
else
out0 <= ~out0;
end
always @ (negedge out0, posedge rst) begin
if (rst)
out1 <= 1'b0;
else
out1 <= ~out1;
end
always @ (negedge out1, posedge rst) begin
if (rst)
out2 <= 1'b0;
else
out2 <= ~out2;
end
endmodule
Which results in the following systhesis (using Vivado for a Zynq-7000):
Note that the FF clock inputs and feedbacks match your expectation for the ripple design.
HDLs are not really designed for rippling designs… as you said rippling designs have no clock, however the concept (in Verilog) is represented by dependency lists.
In short each rippling signal for a construct should go in the sensitivity list.
At least that's my theory I actually never tried it :D
