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I have a VHDL block that implements a state machine, with states defined as a type and the current state as a signal of that type (typical convention).

-- VHDL
type my_fsm_t is (
   idle,
   check_value,
   wait_for_done);
        
signal my_fsm_state : my_fsm_t;

Is it possible to access and use these friendly state enumerations in a SystemVerilog testbench?

// SystemVerilog
let fsm_s = my_tb.my_vhdl_dut.my_fsm_state;
assert(fsm_s == idle) // Fails because it looks for a variable 'idle'

// Modelsim is able to access/interpret some of the state info,
// but not enough to get the enumerated state names
$display("typename(fsm_s) = %s", $typename(fsm_s)); // Works! 'enum bit[0:1]'
$display("fsm_s = %d", fsm_s);                      // Works! '0'
$display("fsm_s = %s", fsm_s);                      // Works! 'idle'

Is there something I need to do with the VHDL my_fsm_t in my SV testbench? It seems like my SV testbench needs more information about the FSM type enumeration.

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  • \$\begingroup\$ VHDL has a better developed type system from the start than the Verilog family. I'm not sure it's reasonable to expect complete compatibility when mixing them, and what compatibility there is may be specific to one simulator. \$\endgroup\$
    – user16324
    Oct 29, 2021 at 17:03

1 Answer 1

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It's possible, but depends on which tools you are using. There is no standard of interoperability between standards like SystemVerilog and VHDL. Modelsim/Questa lets you share data types between languages by putting them in common SystemVerilog or VHDL package, and then importing that package into both languages. Look for the -mixedsvvh switch in the documentation.

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