I am very shocked to see a phase difference between the input and the midpoint of voltage divider. The voltage divider for this circuitry is two 1Mohm in series. The input signal is powered by the function generator @ frequency of 161kHz.

Below is the signal of the input and the midpoint. I used metal film resistor, and I have also tried with an SMD resistor but it still has a phase difference.

What's other shocking part here is the the midpoint voltage is very low - 42.8mV compared to the input voltage of 4.12V. I would assume that since this is a two 1Mohm in series, the midpoint voltage would be half the input voltage.

What can I do to reduce the phase difference between the midpoint and the input voltage of voltage divider?


Measured at the input and the midpoint of a voltage divider (two 1Mohm resistor in series) I don't see a phase difference when I have a 10X probe but the voltage peak to peak of 70mV is low.

With 1X probe enter image description here

With 10X probe enter image description here

PP510 Probe: enter image description here

  • 1
    \$\begingroup\$ Have you considered the input impedance of your oscilloscope and it's capacitance? Move the input probe into the midpoint as well and watch the signal change. Switch the probe to 10:1. \$\endgroup\$
    – Transistor
    Commented Oct 30, 2021 at 1:27
  • \$\begingroup\$ Put the probe back to 10x and you'll get results closer to what you expect. \$\endgroup\$ Commented Oct 30, 2021 at 2:20
  • 1
    \$\begingroup\$ Never use 1x probes unless you absolutely know that you need them, and even then you probably shouldn't. 1x probes have very low input impedance and very poor bandwidth compared to 10x ones; your probe is ruining your measurement. \$\endgroup\$
    – Hearth
    Commented Oct 30, 2021 at 3:27
  • \$\begingroup\$ Sam, yes, you will get the same signal on both probes but you should see a change when you attach the second probe. The point of the test is to demonstrate that the 'scope probe is loading your circuit. Adding a second probe loads it twice as much. \$\endgroup\$
    – Transistor
    Commented Oct 30, 2021 at 8:42
  • 1
    \$\begingroup\$ Your question says 161 kHz but your scope is showing 34.5 kHz so there's something wrong there. At 35 kHz the 'scope's 20 pF input capacitance will look like 230 kΩ and that will be in parallel with the 1 MΩ input resistance. I reckon that should drop your signal from 4 V to 540 mV. You're only getting one tenth of that so there's something else going on. A photo might help. \$\endgroup\$
    – Transistor
    Commented Oct 30, 2021 at 9:03

3 Answers 3


You add a capacitive divider (C1 and C2) in parallel with your resistive divider (R1 and R2) so higher frequencies don't have to deal with the input capacitance (Cinput) only through the divider resistors which results in an RC time constant. They bypass the resistive divider and get stepped down in the capacitive divider.

The input capacitance is probably very small, so if you tried to use it as the lower capacitor in the divider (i.e. a capacitive divider with just C1 and Cinput, without C2) that would probably require an unreasonably small cap value for C1 to get your capacitive divider ratios to match your resistive divider.

Furthermore, is also difficult to measure Cinput and it has loose tolerances and not necessarily high stability which will result in a capacitive divider whose ratio is not accurate and not stable compared to the ratio in your resistive divider.

Instead, you place a good, stable, accurate capacitor in parallel with the input capacitance to swamp it. Then you use that as the lower cap in the divider and choose the upper cap so your capacitive and resistive divider ratios are the same.

This is what it would look like for a 1/11 resistive divider if the Input capacitance was around 5pF (the exact value isn't important as long as you know approximately what it is and choose C2 to completely swamp and dominate it).


simulate this circuit – Schematic created using CircuitLab

If you did not have C2, then for C1 and Cinput to produce a ratio matching the divider, you would need C1 = 0.5pF; An unreasonable value because capacitors that small aren't produced because even traces and wires have more capacitance than that. And even if you were able to accurately measure Cinput and even if you did have a tiny, tiny capacitors and were able to carefully handle the traces to get the correct capacitance at C2, as previously mentioned, Cinput may vary with temperature and other operating conditions.

Since caps have loose tolerances, you may need to include C3 so you can tune the capacitive divider to be an accurate ratio. Reduce C2 when doing so such that C2 + Cin are a bit bit under the value you need, and such that C3 can bring the overall capacitance of the lower half above what you need.

In this way, you do not need to neglect C2 and it will automatically be accounted for when you tune things. Though, you could neglect it if you want since you should be choosing C2 to dominate Cin since it makes the capacitance more stable and all your calculations easier.

Don't forget to account for tolerances when choosing values For C1, C2 and C3. You should be using capacitors with good high frequency response and low DC bias effects for this since they are in the signal path. Like C0G/NP0 ceramic caps. Most other ceramics will shift in capacitance as their DC bias changes.

In case you haven't figured it out yet, you tune it by adjusting until input and output are in phase.

Neat, huh? That's what they do in differential amplifier probes to step down high voltages but not have phase shifts.

I learned that trick here:


  • \$\begingroup\$ +10 :-) Tells why AND how to fix it "properly". \$\endgroup\$
    – Russell McMahon
    Commented Oct 30, 2021 at 23:42
  • \$\begingroup\$ Initially after reading your response, I thought that it was similar to Wheatstone bridge where one branch is would be a capacitive divider and the other branch is the resistive branch. Thank you for adding a schematic. I will test it later. \$\endgroup\$
    – Sam
    Commented Oct 31, 2021 at 4:48
  • 1
    \$\begingroup\$ @Sam, you could test out this circuit by connecting Ch1 as a 1:1 and Ch2 using the modified 10:1 both to the signal source (rather than the divider output). If both signals are in-phase and the same amplitude then your calibration is good. (The signal source amplitude shouldn't vary as much as the divider's when the probes are attached so it will make it easier to see what's happening.) \$\endgroup\$
    – Transistor
    Commented Oct 31, 2021 at 9:11
  • \$\begingroup\$ @Sam, I think you mean Ch2 as 10:1. All OK now? \$\endgroup\$
    – Transistor
    Commented Nov 1, 2021 at 18:54
  • \$\begingroup\$ @Transistor both are in-phase and of same amplitude after changing the CH1 as 1:1 and Ch2 as 10:10. If i do CH2 as 10:1 which to me means that probe is set to 10X but on the oscilloscope the scale is remained at 1x. I got 4.12V for channel 1 and 41.2V for Channel 2 and they remain in-phase. \$\endgroup\$
    – Sam
    Commented Nov 1, 2021 at 18:59

Your high impedance resistive divider is being loaded by excess strsy mid point capacitance to ground. There are several things you can do to improve matters. Which (if any) you pick would be governed by which parameters you are trying to keep and which you can let go.

  • Reduce the impedance of your divider

Dropping the resistor values from 1 MΩ to 100 kΩ will reduce the phase shift by a factor of 10. This will load your signal source more. You could buffer the input to the divider with a unity gain high input impedance amplifier. This would allow you to use an even lower impedance divider, possibly kΩ range, for even flatter performance.

  • Reduce the stray capacitance on the output node

Use a 10x probe to your scope. These are specifically designed to reduce their capacitive loading. A scope input and 1m of cable would have a capacitance of > 100 pF. A 10x probe should be < 10 pF. This should reduce the phase shift by a factor of 10. Alternatively you could buffer the output of the divider with a low capacitance buffer.

  • Compensate the voltage divider

Place a small capacitor across the input resistor to compensate for the expected output capacitance. This can be chosen to reduce the phase shift to zero, but it's sensitive to the amount of load, and if you reduce the load capacitance it can over-compensate and advance the output phase. This will load your signal source more. You could buffer the input to the divider with a unity gain high input impedance amplifier.

Or place larger equal value capacitors of at least 10x the stray load capacitance across both resistors. This lowers the output impedance of the divider at AC, improving the phase shift by 10x or so. It's also tolerant to reducing the load capacitance without over compensating. This will load your signal source more. You could buffer the input to the divider with a unity gain high input impedance amplifier.

  • \$\begingroup\$ I used a 10X probe, and the phase difference has gone down a lot but the midpoint voltage is still low. I have added an image of the result above. I have tried using a voltage divider of 100Kohm instead of 1Mohm, and that seems to work but I would like to use higher resistance. \$\endgroup\$
    – Sam
    Commented Oct 30, 2021 at 23:56
  • \$\begingroup\$ @Sam Not sure why you keep asking people the same question when I already told you what needs to be done. Neil also told you what needs to be done but it's as if you completely ignored what he wrote about adding a capacitive divider.. \$\endgroup\$
    – DKNguyen
    Commented Oct 31, 2021 at 0:03

The probe has capacitance load resistance, and it's not insignificant compared to the impedance of your signal (1M ohm from the source).

Basically, the probe is loading the divider with both capacitance (causing the phase shift and reduced amplitude) and resistance (reduced amplitude.)

More here: Why adding capacitor to a 10x passive oscilloscope probe

To measure such a node, you could use an active, ultra-high impedance probe.


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