# What is the relationship between the number of bits and the sample rate?

Ok, so this topic keeps confusing me. I know that the number of bits is related to the vertical levels. The more bits, the more vertical levels we have. If we have a sample rate of 4 samples per second and a bit depth of 2 bits or 4 vertical levels, does that mean that each sample of these four samples has a height of one vertical level? If that's the case, what happens if we have 3 bits or 8 vertical levels but the same sample rate we don't have enough samples to cover each vertical level?
Does that mean that the first 4 samples cover the firs 4 vertical levels then the next 4 samples cover the other 4 vertical levels in the next second?

• I'm not sure I understand what you're asking. There's no relation between bit depth and sample rate other than in the fact that it's hard (=expensive) to get a high bit depth and a high sample rate at the same time. Oct 30, 2021 at 3:24
• No. Number of levels is independent of samples. Imagine you have a sine wave with 8 levels (3 bits). And the sine wave freq is 1 cycle per second. with sample rate 8 samples per cycle (sec. here). You would have one sample per level. You could have 16 samples per cycle and 2 samples per level. On and on. Levels are the same, samples per level are changing with sample rate.
– pat
Oct 30, 2021 at 3:42
• I think you're all confused. It's simpler than you're making it. Number of samples is like frame rate. Number of bits is like number of pixels in the image (or colour depth if you want). The number of pixels (or colour depth) in the image doesn't change between samples. We could have 11 samples per second and 3 bits per sample, or 3 samples per second and 7 bits per sample. No relation. Oct 30, 2021 at 3:49
• Analog what level is your schooling? Oct 30, 2021 at 5:00
• There is no relation between sampling rate and bit depth.
– User
Oct 30, 2021 at 9:56

What is the relationship between the number of bits and the sample rate?

There is no relationship between the number of bits and the sample rate. They're completely independent parameters. You can have MHz sampling rates at 1 bit, or 20 bit sampling at 1 Hz.

If we have a sample rate of 4 samples per second and a bit depth of 2 bits or 4 vertical levels, does that mean that each sample of these four samples has a height of one vertical level?

No, nothing like that. Each sample could be the same level or they could all be different levels. The levels are what value the signal had at the instant the sample was recorded. More samples per second means you know more time points. More levels means you know each time point more accurately. Since one covers amplitude and the other covers time they're essentially unrelated.

I think you're confused with terminology.

A sample is a snapshot of some waveform, whether it's a particular voltage, or a digital number having some bit depth like 2, or 3 or 8, or 24 bits, and we can use a DAC or ADC to get between one and the other.

If the bit depth N is 2 bits, we can resolve 4 analogue levels, 8 bits resolves 256 levels and 24 bits more than 16 million. We sometimes refer to this group of bits as a word, however many bits there are in it.

The sample rate Fs is the rate at which successive samples occur, when representing a waveform. In audio, it's typically 44.1 ks/s or 48 ks/s. It doesn't matter what the word width is, it's that many samples per second.

In many applications, the digital words are moved around as a word at a time, on a parallel connection. Here the meaning of sample rate Fs is unambiguous.

In many other applications, the digital words are converted to and from a serial stream and moved around a bit at a time. Here the bit rate needs to be at least N*Fs. This rate only exists within the digital part. At the converter itself, the words are handled at Fs.

If your sample rate is Fs and your number of bits is N then your SAR clock or Successive Approximation Rate ADC must be at least N*Fs for an ADC to count all the binary levels from the Analog Sample and Hold value. (S&H)

1st bit comparison is at 50% of full scale and result is 1 if >=50% else 0.
That result is subtracted and the difference is compared with 25% of the full-scale reference voltage (Vref) and selected as a 0 or 1 as before for the 2nd bit. This process is repeated until all N bits are computed before then next sample is taken and the ADC starts all over again with the N bit ADC result in a register.

Of course the ADC clock can be much faster than N times Fs but this is the minimum multiple of the sampling rate.

Allowance for sampling time must also be made or it can have a separate capacitor for ultra high speeds with "track & hold" so the next sample is ready using an analog switch to toggle to next sample to start the same process all over again. Sampling times may be very fast with low drift caps that hold the voltage for the entire duration of the conversion process. This is important and 1/4 second hold times is rather difficult using 4 samples per second so it's easy to use a 1 MHz SAR clock even if the sample rate is only 4 sps.

But the same theory applies to KHz, MHz etc sampling rates.

The next issue is limiting the input BW well below 50% of the sampling rate and below the resolution of the ADC to avoid "aliasing" errors

There are many methods of ADC : Sigma Delta, Flash, IDC, VCO method, but SAR is one that fit the fuzzy question.

• Nice writeup. But there are other types of ADCs other than the SAR you described. Oct 30, 2021 at 21:53
• @SteveSh yes , VCO based, Analog tree Flash 1 cycle converters, Integrate and dump , but I was surmising , he was thinking of this method Oct 31, 2021 at 13:01

I'm going to try to interpret how I think you thought about this question as there were a lot of things you didn't make clear.

I think you are visualizing something close to a perfect ramp going into a converter (let's use an ideal 3bit ADC here). The input range is such that on a time scale and with a periodic sample clock (at a high enough sample rate), there would be exactly 8 samples in the time interval of the input voltage range (coincidence here) which happens within a 1 second window (again coincidence here). And with 3bits or 8 possible levels the conversion might look like this. Where (at least) all 8 levels are uniquely captured in the window, with this exact sampling rate.

"The more bits, the more vertical levels we have. If we have a sample rate of 4 samples per second and a bit depth of 2 bits or 4 vertical levels, does that mean that each sample of these four samples has a height of one vertical level? If that's the case, what happens if we have 3 bits or 8 vertical levels but the same sample rate we don't have enough samples to cover each vertical level?"

In this exact contrived case, there are literally 8 samples corresponding to 8 unique ideal levels of the converter at a height of one vertical level each -- and within a range of a 1V input (coinciding with a time window of 1sec). Having a lower sample rate with this configuration you would obviously miss some of these ideal levels in the single window of the ramp.

Your question then is... "Does that mean that the first 4 samples cover the first 4 vertical levels then the next 4 samples cover the other 4 vertical levels in the next second?"

Not really in this case, nor in general.

But... there might be a sample impoverishment if my sample rate isn't high enough to capture all the levels in the sample window. How could I capture the other levels I missed?

So, first I'll say this. If we were to assume a perfect sine wave in the window with all the same conditions, you would not get all 8 unique levels covered as you did with the ramp. This is because a sine wave does not have a linear relationship with the conversion range as the ramp did. So you might get some repeated levels and miss some even with 8 (2^N) samples of a periodic sine in one window, perfectly spaced.

Second and more importantly is that nyquist criterion tells us that we don't even need 8 (2^N) perfect samples in a periodic window to capture the proper levels of our converter. It guarantees that as long as the sample rate of our converter is greater than twice the highest input bandwidth, over the long run we will accurately capture a resolution of 2^N levels. That means you can miss several levels in one period and come out fine, but with many, many samples you will capture all of the levels over time (and avoid aliasing).

Practically, speaking we will take a lot of samples (more the better) a bit higher than twice the nyquist rate and our samples will be staggered somewhat so we will end up capturing enough sample points and levels that will accurately cover our converter rate and range. When we take an DFT/FFT of captured sampled data, to look at the dynamic performance of the converter, we have to be careful to take into account how exactly we sampled relative to the input window and the width of the window, etc.

Some people might comment that a ramp is not a sine, and doesn't follow, but my point was to make a simple and (hopefully) intuitive analogy to the op request.

Ideally as others already noted, we would like to have a very high sample rate and very high resolution (which is costly and they usually don't go hand in hand). And as long as we follow nyquist criteria we should be ok. disclaimer. There are even undersampling architectures, but that's beyond the scope here.

Also, as others noted there are all kinds of architectures. Some are serially processed 1 or more bits per clock cycle (e.g. pipeline), some process all bits once per cycle (e.g. full flash), and others can only have 1 bit of resolution at a very high oversample rate, yet capture a very high effective resolution (e.g. sigma delta). So they aren't all restricted to one form by any means.

The only “relationship” between the two is that you can multiply them to get the total bandwidth (in bits per second).

So one isn’t dependent on the other, quite the contrary, they are orthogonal, and together they can define another value.

If you have one sample per second and one bit per sample, then you have a total of 1 x 1 = 1 bit per second.

If you have 1 million samples per second but still only one bit per sample, you get 1 million bits per second.

If you have one sample per second but 8 bits per sample, you get 8 bits per second.

And if you have 1 million samples per second and 8 bits per sample, then you have 8 million bits per second.

“Samples per second” can be used for measures (e.g. an ADC or an oscilloscope measuring that many times per second) or for data transmitted (and of course received, which brings back to the first case), though in the case one would usually say “symbols per second”, but in the end it’s the same thing.

In the latter case, “samples per second” is like the number of vehicles per second crossing a line, while “bits per sample” is like the number of people in each car. They are obviously completely independent. But if you multiply them together, then you get the total number of people crossing the same line each second.