How to calculate rise time for SPI and UART

I am trying to calculate rise time for SPI and UART.

SPI: I know that the rise time is related to the external capacitance on the bus, so in a datasheet it's specified for a specific loaded capacitance. How do I take this and use this to determine the rise time for any other capacitance? Do I just treat the specified rise time as an RC value?

There is another question on this, but they don't show or explain how to actually calculate this: Computing Rise Time on SPI Bus

One of the answers implies that you should think of the rise time on an SPI bus in the same way as a discharging RC circuit, so you have an output R and external C that together determine the rise time that is specified in the datasheet. That would mean, in the case of a PIC32 MCU, that the 50 pF load impedance and 5 ns rise time specifications are defined for a driver with 100 Ohm output impedance and 33 mA output current (assuming 3V3 logic level). Is this correct? Seems like it might be wrong, I would have expected under 50 Ohms output impedance.

UART: With UART, I have no idea where to start, I can't find anything on the internet that talks about rise/fall times. Do they even matter? Is it the same idea as with SPI?

• 50pF and 100Ohms makes a time constant of 5ns. Not a risetime of 5ns. The rise time would be something like 3 to 5 time constants depending on where you want to draw the line. Oct 30, 2021 at 5:57
• Yes I see that, so if I take factor 2.2 for a 90%-10% rise time, that gives a 45 Ohm output impedance. Is that correct? Or is that for the trace impedance + driver impedance in this specific spec? Oct 30, 2021 at 5:59
• Actual rise time is affected by all the impedances present, drive output impedance and line impedance. In reality, there's also transmission line effects (reflections and junk) and then things get messy. Oct 30, 2021 at 5:59
• Sure I understand that, the end goal here is to figure out when source termination will be needed, but I would want to get the rise time first. Based on what I just calculated, it appears 45 Ohms is source + trace impedance within this specific spec. Is that how you're reading the calculation? Oct 30, 2021 at 6:02
• Yes............ Oct 30, 2021 at 6:04

SPI can go up to 60 Mbps and matching the driver source impedance is necessary for the highest immunity to reflection noise at 5 ns/m for most plastic cables and PCB epoxy fiberglass.

Even with a matched R source and stray capacitance of a few pF on the load with high impedance will result in perhaps 20 to 30% overshoot ringing for a half dozen cycles at cable resonance.

Risetime is technically defined by 10 to 90% of the endpoints and the noise near the threshold voltage during the clock transition actually is all that matters. But random noise, and echo noise can add up.

Slew rate is the initial RC=T to the asymptotic 63% of target determined chiefly by Vol/Iol=Rol and same for (Vdd-Voh)/Ioh=Roh but the Nch and Pch are designed to match but may have 25 to 50% tolerances depending on CMOS type and supply voltage.

for 5V SPI I would assume from the past Ro=22 Ohms and add something close to 28 Ohms for 50 Ohm cable and 200 Ohms for 220 ohm cable. Although 3.6V logic is lower R than 5.5V logic you can compute from the end of your datasheet specs and 25% tolerance is often acceptable.

If the risetime is approaching faster than the delay time then echos will occur but not matter with spike overshoots but when the creep towards the middle of the data bit you want to be sure you have the signal integrity you need for the added ambient noise that may exists. So an improvement might not be necessary but it would be a pull up+down resistor to have the equivalent match to the cable R for clock and data.

Although in an environment of high common mode noise, ( like my coffee maker thermal regulator switch, a recent question on laptop noise on a UPS interfering with LEDs ( recent question on noise) where you expect error-free communication the wiser choice would be to convert to differential logic with LVDS. on a shielded cable.

Even more details.

Although it is true that TRANSMISSION LINE effects occur from DC to any frequency, they are not visible when the spectrum is greatly attenuated or slew rate is well below the cable delay time. f-3db = 0.35/Tsr (10~90%)

If you examine the datasheet Vol/Iol that is your driver impedance, If you use 220 twisted pair cable then you might be adding 200 ohms to match the cable to get a good signal, but if there is any parasitic capacitance at the end even 1pF is going to cause noise. Again the most critical zone is noise around the data middle where Re-sync of data and clock edge occurs, so it is wise for signal integrity reasons to use an active pullup to the average DC voltage of the data threshold or a pull up+down to match the cable impedance.

Here are two examples using a 3 GHZ DSO simulation of of 10 MHz on a 1 m cable with different impedances. The overlapping 3 traces include the input, output and the echo back at input.

The middle trace is terminated with a faint plot of a well-damped signal response at 50 Ohms. The same effect occurs with 220 Ohms.

The lower trace is unterminated. It looks worse with a 1pF load and effects increase with this parasitic pF load as even 1pF with 0 ESR appears as a short circuit to the edge wave with full spectrum.