I have just learned about how logic gates work and I am trying to simulate a 1-bit register without using a clock signal. My design looks like this:

1-bit register

The logic should work something like this (psudeocode):

if(Change) R0 = B0
else R0 = previous R0

(truth table):

1-bit register truth table

However, when I try this on different simulators, I get mixed results:

  • It DOES work on the Academo logic gate simulator
  • It DOES NOT work on the CircuitVerse logic gate simulator OR the Deeds logic gate simulator

Will this logic design work in real life or not?

  • 3
    \$\begingroup\$ Very carefully analyse what happens on transitions of change. On a rising edge, momentarily, both change and !change will be 1, and on a falling edge, both 0 (for the duration of a gate delay). What happens then? (You can incorporate !change into the truth table, to assist with this) Good question though. \$\endgroup\$
    – user16324
    Commented Oct 30, 2021 at 22:56
  • 1
    \$\begingroup\$ Thanks for your help! I'll give that a go today. Is that because the new "Change" signal reaches "ChangeB0" before the new "Change'" inverted signal reaches "Change'R0"? Meaning the old "Change'" signal is still used at the same time as the new "Change" signal? \$\endgroup\$
    – JD9999
    Commented Oct 30, 2021 at 23:10
  • \$\begingroup\$ Have you seen this, and the methodology used for knowing the behavior of asynchronous circuits ? ee.ucl.ac.uk/~ademosth/E757/Topic6.pdf See an example of my answer at electronics.stackexchange.com/questions/591677/… \$\endgroup\$
    – Antonio51
    Commented Oct 31, 2021 at 10:35
  • \$\begingroup\$ @JD9999 Exactly. A good simulator allows you to annotate gate delays, such as !change = not change after 3 ns; to model the inverter : without knowing the simulators you use (there's a reason I'm a VHDL guy) this is likely to be teh reason your sim results are different. \$\endgroup\$
    – user16324
    Commented Oct 31, 2021 at 13:14

2 Answers 2


Very good subject considering you've just started! Yes, that is indeed used in "logic programming". In the "Relay Logic" that is called "self hold", which does a controlled latch/register using logic elements.

In hdl forms: Q = Q & C + A, where Q latches A = 1 until C = 0 clears.

For your logic, A is gated by change: R0 = (R0 & /CHANGE) + (CHANGE & B0)

The problem is that the occurrences of the logic output change are not simultaneous (though still problematic), but affected by "propagation delay". In your circuitry, while assuming all the logic elements have the same delay, withdrawal of CHANGE already affects the R0, before it gets latched in [change'R0] loop.

Thus, we may insert a delay line (a few more gates) in between CHANGE & [ChangeB0], so the [Chage'R0] output establishes before the withdrawal of CHANGE appears at R0.

Meantime, relying on propagation delay is considered not safe, though it works, due to the analog nature of the propagation delay. Solution to that is using multistage latches.

Delay line example


simulate this circuit – Schematic created using CircuitLab

Multi stage example


simulate this circuit

B0 is "gated" with Change at the AND1 & AND2, since that is when the change occurs. NOR1 & NOR2 are RS-Flip Flop (Set and Reset), which is a double side self-hold.

  • \$\begingroup\$ I tried adding different gates: a buffer, a AND (Change, Change) and an OR (Change, Change), but the result is still the same. How do I do the delay line properly? \$\endgroup\$
    – JD9999
    Commented Nov 1, 2021 at 5:40
  • \$\begingroup\$ @JD9999, The delay depends on the realization of the circuitry. It could be real circuitry, FPGA, PLD, PLC programming, or could be just for simulation. In case of real circuitry, multiple factors have to be considered to have enough "operations margin", and, sometimes, it may need to be clocked. If you can describe the actual applications, if you have any, that will help getting better answer. \$\endgroup\$
    – jay
    Commented Nov 1, 2021 at 16:25
  • \$\begingroup\$ @JD9999 , In addition to the propagation delay, If you continue progress, you will reach to some questions like this. \$\endgroup\$
    – jay
    Commented Nov 1, 2021 at 18:19

For reference, https://www.ee.ucl.ac.uk/~ademosth/E757/Topic6.pdf

Also example, How does an SR-latch actually work?

Unless I am wrong, here is the K-map of your ckt.

enter image description here

Ch stand for Change, BO, Q2 stand for R0 output, q2 stand for Previous R0. Change only C or BO, at one time, and follow what is in the case choosen.

If "stable state", remain there, if "unstable state" change line.

Example: starting from (q2,Ch,BO)=(1,1,1),

change B0=0, so first go to right in case (1,1,0) where you read 0 (instable),

so must change line to (q2)=(0) ... go to (0,1,0) which is stable.

Illustrating what to do with asynchronous circuits ...

enter image description here

Obviously, it is better to use digital circuits synchronized by a clock and using, for example, D MS-FF, so using in fact FSM methods.

For some kind of circuits, you can use multiplexers (2^n inputs to 1 output) as "generating" the function. In this case, the delays are ... "equal", ... except for the decoding scheme. To try.

  • \$\begingroup\$ Thanks for your answer! That document you attached looks really helpful, I'll have a better look at it after my uni exams. I tried adding a buffer (in the Deeds simulator), however I still have the same issue I had before. In real life, can a buffer and a not gate from the same manufacturer/product line be expected to have the same delay times? And since S-R latches have the inputs pass through the same number of gates, does this make them immune to the kind of issue I'm having? \$\endgroup\$
    – JD9999
    Commented Nov 1, 2021 at 5:33
  • \$\begingroup\$ First question, yes, I think so, delays can be equal, just a question of "topology". Other question, Problem of RS having same number of gates have to be resolved with adding more internal variables ( 2 for RS latch in this case, 2 "equal" delays, K-map of 4 variables inputs : R, S, q1, q2, 2 ouputs Q1 and Q2). I have made such study for D master/slave FF somewhere in this site. \$\endgroup\$
    – Antonio51
    Commented Nov 1, 2021 at 9:17
  • \$\begingroup\$ See my answer electronics.stackexchange.com/questions/205761/… \$\endgroup\$
    – Antonio51
    Commented Nov 1, 2021 at 14:29

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