Will this register drawing work?

Question

I have just learned about how logic gates work and I am trying to simulate a 1-bit register without using a clock signal. My design looks like this:

The logic should work something like this (psudeocode):

if(Change) R0 = B0
else R0 = previous R0

(truth table):

However, when I try this on different simulators, I get mixed results:

• It DOES work on the Academo logic gate simulator
• It DOES NOT work on the CircuitVerse logic gate simulator OR the Deeds logic gate simulator

Will this logic design work in real life or not?

Answer 1

Very good subject considering you've just started! Yes, that is indeed used in "logic programming". In the "Relay Logic" that is called "self hold", which does a controlled latch/register using logic elements.

In hdl forms: Q = Q & C + A, where Q latches A = 1 until C = 0 clears.

For your logic, A is gated by change: R0 = (R0 & /CHANGE) + (CHANGE & B0)

The problem is that the occurrences of the logic output change are not simultaneous (though still problematic), but affected by "propagation delay". In your circuitry, while assuming all the logic elements have the same delay, withdrawal of CHANGE already affects the R0, before it gets latched in [change'R0] loop.

Thus, we may insert a delay line (a few more gates) in between CHANGE & [ChangeB0], so the [Chage'R0] output establishes before the withdrawal of CHANGE appears at R0.

Meantime, relying on propagation delay is considered not safe, though it works, due to the analog nature of the propagation delay. Solution to that is using multistage latches.

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Delay line example

^{simulate this circuit – Schematic created using CircuitLab}

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Multi stage example

^{simulate this circuit}

B0 is "gated" with Change at the AND1 & AND2, since that is when the change occurs. NOR1 & NOR2 are RS-Flip Flop (Set and Reset), which is a double side self-hold.

Answer 2

For reference, https://www.ee.ucl.ac.uk/~ademosth/E757/Topic6.pdf

Also example, How does an SR-latch actually work?

Unless I am wrong, here is the K-map of your ckt.

Ch stand for Change, BO, Q2 stand for R0 output, q2 stand for Previous R0. Change only C or BO, at one time, and follow what is in the case choosen.

If "stable state", remain there, if "unstable state" change line.

Example: starting from (q2,Ch,BO)=(1,1,1),

change B0=0, so first go to right in case (1,1,0) where you read 0 (instable),

so must change line to (q2)=(0) ... go to (0,1,0) which is stable.

Illustrating what to do with asynchronous circuits ...

Obviously, it is better to use digital circuits synchronized by a clock and using, for example, D MS-FF, so using in fact FSM methods.

For some kind of circuits, you can use multiplexers (2^n inputs to 1 output) as "generating" the function. In this case, the delays are ... "equal", ... except for the decoding scheme. To try.