# What's the use of a decoupling capacitor near a reservoir capacitor?

I've seen some circuits where a decoupling capacitor is used as well as a reservoir capacitor, like this (C4 and C5):

I've read about decoupling capacitors and for me it looks as if they are meant to remove small fluctuations in the supply voltage. Then I thought - wasn't that the purpose of a reservoir capacitor as well? Why wouldn't the reservoir capacitor be able to filter out the small fluctuations, if it is able to filter out the large fluctuations?

So I feel like I have a basic misunderstanding here. What is the purpose of a decoupling capacitor next to a reservoir capacitor, when we assume we place both equally near to the power consuming part? Or is the only advantage of the decoupling capacitor that it is smaller and can therefore be easily placed more near to the power consuming part?

• Camil, don't worry about it. As @m.Alin said, it is good to wait a day or so to see what answers collect before deciding on the one that you want to accept. I know that I often skip over questions that have accepted answer, since they are "done" and my time is better spent elsewhere. I expect others do this too. Don't forget to accept my answer later though :-) – Olin Lathrop Feb 27 '13 at 18:58
• Near-duplicate question: electronics.stackexchange.com/questions/25280/… – The Photon Feb 27 '13 at 22:58
• When reading the answers, remember that you can get 0.1 uF as a ceramic in an 0402 package, but 100 uF will probably be an A-size electrolytic or bigger. – The Photon Feb 27 '13 at 23:02
• – endolith Feb 28 '13 at 0:47
• – Keelan May 17 '13 at 6:33

The most likely reason why that is done is because, in real life, capacitors do not have infinite bandwidth. Generally, the higher the capacitance of the capacitor, the less it will be able to react to high frequencies, while small-valued capacitors react better to higher frequencies, as seen in the graph below. Using two different-valued capacitors together is just done to improve the response of the filtering.

• This is a nice chart. I wonder what 100uf would look like on it (it kinda looks like there is no point to use a 100nf cap!). And, where did the graph come from? – Bobbi Bennett Feb 27 '13 at 18:17
• @Bobbi 0.1 uF = 100 nF – m.Alin Feb 27 '13 at 18:23
• @m.Alin, notice that there is only one tiny part of the spectrum where 0.1uF has lower Z than 2.2uF? I imagine a 200uF with its series impedance would be quite a bit higher than 0.1 Ohm at 10 Mhz, but it isn't on the chart. – Bobbi Bennett Feb 27 '13 at 20:13
• @BobbiBennett you're right, there seems to be almost no advantage of 100nF when you compare it to 2.2uF. However, do keep in mind that this is a logarithmic chart so the advantage is bigger than you'd say. Also, the size of a 100nF could be an advantage. – Keelan Feb 28 '13 at 10:28
• This chart shows different values in same package. 100 uF will likely come in a larger package, so the inductive curve will be further to the left. 0.1 uF is likely available in a smaller package, which would move its inductive curve further to the right. – The Photon Apr 21 '13 at 17:23

As you say, a decoupling cap and a power supply bulk reservoir cap serve two different purposes. You are correct in that the decoupling cap needs to be physically close to the consumer of the power it is decoupling. The bulk cap can be anywhere on the power net since it deals with low frequency currents.

However, the incorrect assumption you are making is assuming schematic placement implies physical placement. It doesn't. In a good schematic, there will be some hint to physical placement. In this case we can't tell if if the decoupling capacitor (C5) is physically near IC1 (where it should be) or not.

Personally I wouldn't draw a schematic this way for exactly this reason, and I think doing so is irresponsible. However, the schematic capture software will generate the same net list either way, so the details are really up to placement. Without a board layout diagram, you simply can't tell. I usually draw the decoupling caps physically close to their parts to give a hint that this is what I intend and that I've thought about it. This is one issue I mention when talking about how to draw good schematics at https://electronics.stackexchange.com/a/28255/4512.

Unfortunately, there are a lot of badly drawn schematics out there.

• There are a lot of badly-drawn schematics to be sure, but I would expect a good board designer to know how to layout bypass caps regardless of physical placement on the schematic; placing bypass caps near components may sometimes be helpful, but in some other cases it just adds clutter. – supercat Feb 27 '13 at 20:11
• @Supe: As long as the board designer knows they are supposed to be bypass caps. If you don't point this out somehow, you're taking your chances. Sometimes the bypass caps can add clutter and you can put them off in a corner, but then at least put a note there explaining that. – Olin Lathrop Feb 27 '13 at 20:14
• When coupling and decoupling issues are essential to the performance of a design, I would never assume that the board designer would know what to do about placement without being told explicitly. +1 to Olin's answer just for pointing that out. -1 to supercat for suggesting anything different. (Bad cat!) – Jim Feb 27 '13 at 21:02
• When we say that the bypass capacitors should be close by, how much will the distance realistically affect it? Is there any study or some tests done? Is the main problem the resistance of the track or capacitance of the track or something else...? Is it to minimise the EM interference? – midnightBlue May 30 '14 at 3:04
• @midn: The main issue is the inductance of the tracks. – Olin Lathrop May 30 '14 at 11:06

When two or more decoupling capacitors of different values are used in parallel, it is necessary consider the parallel resonance that occours between the two networks.

Clayton Paul described this phenomena. Consider a parallel coupling of capacitors C1, C2, with different values and C1>>C2 with parasitic L1 and L2 about the same L1=L2 (figure 1.A).

We suppose $f_1$ is the frequency where the capacitor C1 is resonant with inductor L1, and $f_2$ the frequency where capacitor C2 is resonant with inductor L2.

Below the frequency $f_1$ both networks look capacitive, and the total capacitance is equal to the sum of the two capacitors. This improves (very little) the decoupling at the frequencies below $f_1$.

Above $f_2$, both networks look inductive and the total inductance is equal to the two inductors in parallel, or one half the inductance. This improves the decoupling at frequencies above $f_2$.

At a frequency between the resonances of the two networks ($f_1 < f < f_2$), the equivalent circuit of the two networks is a capacitor in parallel with an inductor, as shown in figure 1.b (parallel resonant circuit). This produces a resonance (figure 2), which becomes a problem when the tolerance of components are over 50%.

Therefore, we can conclude that the decoupling will be improved at frequencies above (and under) the frequency at which both capacitor networks are resonant.
The decoupling will actually be worse at some frequencies between these two resonance frequencies, because of the impedance spike caused by the parallel resonant network, which is bad.

The main difference in small capacitors and large electrolytic capacitors is their frequency response. Electrolytic capacitors have poor specifications for higher frequencies and may eventually fail because of being stressed by the high frequency noise. In turn, high frequencies that the electrolytic capacitor only partially filters, may well be in the upper audible range of your amplifier.

The small capacitor easily filters the high frequency noise, but of course has little effect when it comes to low frequency mains power supply ripple filtering.

Not all capacitors are created equal... The larger bulk capacitors cannot respond as quickly due to ESR and ESL (Equivalent Series Resistance and Inductance) which is dependant upon their make-up.

There is of course the ability to get close like you mention, but in general a good scheme will have bulkier, slower and larger capacitances the further you get away from the circuit. the corresponding frequencies that need to be dealt with also drop, if done properly.

What limits the small decoupling capacitances is the self-resonance of the cap itself and the inductance of the bond wires in the package (again depending upon the package).

This scheme of hierarchical scaling continues inside the IC with critical nodes having local capacitors for higher frequency events. Of course these cap on the inside are the most expensive and smallest of all.

## protected by W5VO♦Feb 27 '13 at 22:59

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