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I have some RGB LEDs that are driven by the popular WS2811 chip made by World Semi. Datasheet is here.

I find the following to be true:

  • The datasheet says that the chip includes an oscillator running at 800 Khz.
  • The datasheet specifies that to transmit a single data bit to the chip (either a 0 or a 1), you need to hold the data line high for a specified time, followed by holding it low for a specified time.
  • The time taken to transmit a single bit is roughly 1.25 microseconds (usec) (roughly).
  • One bit per 2.5 usec gives you a data rate of 800 Khz.

So, whether you are transmitting a 0 or a 1 makes no difference for my question, only suffice it to say you need to "measure" how long the data line is held high. But the oscillator runs at 800 Khz. So, I'm confused: how can the chip determine the length of time you hold the data line high, in order to determine whether you communicated a 0 or a 1, while the oscillator is only running fast enough to read the line once per clock cycle? Seems like the clock needs to run at least double speed to just read the data line twice per data bit, yet even faster than that to read whether the high voltage time is either short or long!

Simply put, how does the chip read bits from the data line at 800 Khz (while the data line needs to be held high and held low) yet the clock only runs at 800 Khz?

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2 Answers 2

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The 800 kHz oscillator may not relate in any way to the data communication. There is no indication in the datasheet that would give an assumption that it does.

As the datasheet does not say anything about it, the 800 kHz could just be the frequency for driving the PWM modulator, and it could already be a divided down from a higher frequency clock.

The data transmission could simply use some kind of delay stage to trigger on rising data pin edge and latch data pin value in after the delay. Then the data pin either is still high or has gone low when the latch happens. I don't say this is necessarily true, but the timing information given in the datasheet seems to indicate that the logic 0 and logic 1 is determined by how long the high pulse is. Most likely we will never know how the chip works internally.

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By utilizing a phase locked loop (PLL) circuit on the chip, it can detect and track the incoming frequency (400 or 800 kHz), then use this to produce internally faster clocks by which it can measure single bit changes.

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