I have a PCB with 60 or so traces in a parallel geometry such that the traces are connected in an alternating pattern as in the picture. My question is, what is the correct way to calculate the total capacitance of this board? My first thought is to treat each pair of traces as a capacitor in parallel with the next pair.The PCB is FR4 if I should consider the dielectric constant. enter image description here

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    \$\begingroup\$ On one hand, I liked "dialectic constant" very much, and want to discuss it. On the other, I fixed a typo in "dielectric constant" :) \$\endgroup\$ Commented Nov 3, 2021 at 0:25
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    \$\begingroup\$ @MarcusMüller Okay. Let's discuss... The Hegelian dialectic [of] constant conflict is ridiculous as it proposes that the continual conflict between extreme belief systems will eventually lead mankind towards a final perfection. ;) \$\endgroup\$
    – jonk
    Commented Nov 3, 2021 at 0:48
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    \$\begingroup\$ What Hegel could not see, of course, was the later constant dialectic of simulation versus rule of thumb; two concepts competing for highest utility for the engineer. \$\endgroup\$ Commented Nov 3, 2021 at 0:50
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    \$\begingroup\$ @MarcusMüller :):)!! \$\endgroup\$
    – jonk
    Commented Nov 3, 2021 at 0:51
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    \$\begingroup\$ (Michael, seriously, if I wanted to produce a 2D structure where I'd guess all the boundary effects add up so significantly that you can't treat this just as a bunch of parallel conductors in average-\$\varepsilon\$ environment, it might very well look like this. Either someone did a lot of math or simulation to come up with a formula for these interdigital traces structure, or this will need to be FEM-simulated) \$\endgroup\$ Commented Nov 3, 2021 at 0:52


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