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For my project I have to design an voltage stabilizer with 5V on input and 3.3V on output.In order to do it , I selected a Zener diode for my reference (D1 and R1) , A divider for negative reaction (R7+R6),current limitation(Q7 +R9) and an error amplifier ( I must use discrete components only ) . On my design I can't make the output voltage to be higher than 1.2V when R3 is almost 0 . I used Vbe=0.6V and Ic=2mA for bipolar transistors . IRFRU120N represents a MOSFET type N as my series regulator element. (1-Drain, 2-Gate, 3-Source).

In order to rise the output i tried to : redimension the divider and adjust every single resistance but nothing happened .

How can I rise the output ? Is something wrong with my design? What can I change on schematic to make it work properly ?

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    \$\begingroup\$ IRFRU120N represents a MOSFET type N as my series regulator element. What you should try: copy that schematic, remove everything except V1, U1, R9, Rl, R7, R6. Then put a voltage source on the Gate of U1. What voltage is needed to make U1 conduct such that you get the output voltage you want (3.3 V) while making Rl so low that the desired load current is flowing. My guess is that you will need almost 5V, maybe more than 5 V at the Gate of U1. Can your circuit create that voltage at the Gate of U1? \$\endgroup\$
    – Bimpelrekkie
    Nov 3, 2021 at 20:46
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    \$\begingroup\$ Take a look at the IRFRU120N datasheet, page 2, look at the \$V_{GS(th)}\$ parameter. Note you are using an NMOS as a Vcc pass element - it is turned on from voltage between the source and gate, but the source will vary as the load varies. \$\endgroup\$
    – rdtsc
    Nov 3, 2021 at 20:50
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    \$\begingroup\$ When I design an (on-chip) LDO above test is what I do first to determine what size my pass transistor needs to be. I might find that it cannot be done, that an NMOS will never be able to do this unless I apply a gate voltage that is higher than the supply voltage (more than 5 V). That's because here the NMOS is used as a source follower so it will drop at least \$V_{threshold}\$. That's why in an LDO you're usually forced to use a PMOS. \$\endgroup\$
    – Bimpelrekkie
    Nov 3, 2021 at 20:50
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    \$\begingroup\$ The MOSFET Vth voltage is around 2V. And this is why you can't get 3.3V at the output. Also with 2.7V Zenera and R7 = R8= 5k you want to forced 2.7V * (1 +R7/R6) = 5.4V And this is impossible for Vin = 5V \$\endgroup\$
    – G36
    Nov 3, 2021 at 20:51
  • \$\begingroup\$ @Bimpelrekkie : remove everything except V1, U1, R9, Rl, R7, R6. I put U2=7V at Gate and the output changed to 3.3V . Now i need change my error amplifier to make it like a voltage multiplier in order to respect the amplifier block ? \$\endgroup\$
    – Luca
    Nov 4, 2021 at 8:57

1 Answer 1

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Is something wrong with my design?

Your output design uses an N channel MOSFET wired as a source follower and, that is the main problem because your input supply is only 5 volts but you require that the source output be at 3.3 volts. The IRFRU120N has a gate threshold voltage of 2 volts minimum and so typically this might be 3 volts. This means that the gate needs to be about 3 volts higher than the source voltage but, that means at least 6.3 volts and this is higher than 5 volts. And, this will only be good with very light loads. Ideally for decent load currents, the gate needs to be 4.5 volts higher than the source.

Do you see the problem?

Also, your regulating voltage is going to be 2.7 volts as defined by the 2.7 volt zener diode, D1.

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