0
\$\begingroup\$

If you have a sequential circuit in verilog or system verilog and want to synthesize it to specific gate types and flip-flops, how do you go about it. For example, may be synthesize the design to nor, and, or, nand, not etc. and flip-flops to use should be say a D flip-flop.

Secondly, how do you get yosys to optimize the designs.

\$\endgroup\$
2
  • 1
    \$\begingroup\$ Last I heard, the target output of synthesis isn't something you just specify in a standard declaration file of some kind. It's the result of hard work and custom coding efforts. I certainly haven't encountered a case in my limited experience where I could say, "target 7400 series for me, please" and it would do that. Let alone floorplan it. I don't know about yosys, but if it is open source then you might have a chance by learning it and then modifying the translator code going from internal structures to target output. I'll be interested if anyone has a useful answer here. \$\endgroup\$
    – jonk
    Commented Nov 4, 2021 at 17:17
  • \$\begingroup\$ I doubt the standard tools are flexible enough, as these are usually targeted at a specific technology. But if you are curious, you can look at these course series, which if I recall correctly, has some programming projects doing stuff close to what you are asking about: coursera.org/learn/vlsi-cad-logic \$\endgroup\$
    – Eugene Sh.
    Commented Nov 4, 2021 at 17:36

1 Answer 1

Reset to default
2
\$\begingroup\$

Yes, you can do this using gate level synthesis in Yosys. You need to create a cell library, containing the elements you wish your Register Transfer Level (RTL) code to be synthesized to. Gate level synthesis converts RTL code to a gate level netlist. This netlist can be written to a Verilog file and can also be displayed.

We use scripts in Yosys to run synthesis. Using the synth command in Yosys you can select the optimizations you want like FSM optimization, arithmetic optimizations, etc.

Refer to the Yosys documentation for more details on this. (https://github.com/YosysHQ/yosys)

\$\endgroup\$
6
  • \$\begingroup\$ All of the application note links at the documention site are broken. That's not sounding good to me. I would really like to read them because your answer is quite interesting to me. (I may be able to find them with the 'wayback machine' of course. But the fact that the links are NOT being maintained tells me a little something about the project, itself, and the energy being sustained for it. Though the dates on some of the files in the github complicate that conclusion a bit.) Glad to see the answer though. So I shall +1 it. It's direct/ontopic. \$\endgroup\$
    – jonk
    Commented Nov 4, 2021 at 18:50
  • 1
    \$\begingroup\$ @jonk The docs are available in the github repo, under "manual" folder. It' just that you'll have to build them from tex.. \$\endgroup\$
    – Eugene Sh.
    Commented Nov 4, 2021 at 20:01
  • \$\begingroup\$ @EugeneSh. Thanks. And I could also get them from the wayback and .tex also works for me. But the fact that their main documentation site has every single application note link broken tells me no one is reading that site and trying to access the application notes. I don't like the implications of that. \$\endgroup\$
    – jonk
    Commented Nov 4, 2021 at 20:11
  • \$\begingroup\$ @jonk I understand what you are saying. But looks like the repo keeps getting updated, so it is not totally abandoned. \$\endgroup\$
    – Eugene Sh.
    Commented Nov 4, 2021 at 20:12
  • \$\begingroup\$ @EugeneSh. Yeah. I saw that, too. Just a source of mixed signals to me. \$\endgroup\$
    – jonk
    Commented Nov 4, 2021 at 20:25

Not the answer you're looking for? Browse other questions tagged or ask your own question.