In Lattice Diamond, spreadsheet view where I assign the signals to pins of the FPGA chip, there is IO type. Restricting the discussion to single-ended CMOS signals, then my choices are given by the voltage level: LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25 (which is the default), and LVCMOS33.

In all the tutorials I've seen, they just stay away from this issue, usually saying that leaving it as LVCMOS25 works (which it does).

I have a design (with an XP2-8, BGA256) where one bank has a 3.3V Vcc, and all the other banks use 1.8V. All of the IO Types are set to LVCMOS25.

What's the relevance of the different IO Types? Any benefit to matching the IO type to the corresponding VCCIO voltage? (i.e., set LVCMOS18 for all pins that are part of a bank powered by 1.8V, and LVCMOS33 for the pins in the bank that uses 3.3V)

Any risks? (for example, is it a problem if I select LVCMOS18 for some of the pins but leave the rest with its default LVCMOS25?)

I'm tempted to "do the right thing" and use the appropriate type to match the VCCIO ... but then, I'm rather worried about changing something that has been working "like a charm" (at least it appears to be working like a charm)

  • \$\begingroup\$ Why do you bother, unless you need to match the IO to attached devices? There is no wrong, neither right, besides minor relevance to speed and power dissipation, I guess. \$\endgroup\$
    – jay
    Commented Nov 4, 2021 at 20:27
  • 1
    \$\begingroup\$ @jay ‒ what do you mean by "unless you need to match the IO to attached devices" ? The IO pins are certainly attached to some devices; and surely enough, the voltage levels need to match. In our case, the pins from banks powered at 1.8V are connected to an MCU which has VDDIO=1.8V. The 3.3V bank is for LEDs. What keeps nagging me is: if it is at best marginally relevant, why do we have all those options? \$\endgroup\$
    – Cal-linux
    Commented Nov 4, 2021 at 20:45
  • \$\begingroup\$ Ha ha.. Very intriguing reasoning.. no kidding, no offense, sincerely. I respect and like to learn different angles of view. So, why is the relevance of "IO voltage matching" marginally meaningful, but not the most? \$\endgroup\$
    – jay
    Commented Nov 5, 2021 at 18:11

2 Answers 2


The actual design of the IOB is proprietary, so it is necessary to speculate and infer from other designs. I'll speculate based on both Xilinx parts which I know best, and some of Lattice's own documentation.

First, in many cases, the input standard you use doesn't have to match the actual VCCIO supplied to the bank. For example, a Xilinx spartan-6 IOB (see table 1-5 in this) will happily support inputs that use e.g. LVTTL, LVCMOS33, and LVCMOS18 on a bank with a 2.5V VCCIO and without an additional reference voltage, as long as the configuration properly indicates the correct bank voltage for each bank and the correct signalling standard for each pin.

Of course, it cannot drive outputs without the correct VCCIO as it has no power rail to drive from.

Second, there are plenty of ancillary functions onboard an IOB in output mode which are dependent on the actual selected IO standard, such as drive strength and slew rate. Referencing this lattice document, you can see that even "similar looking" standards like LVCMOS33 vs LVCMOS25 vs LVCMOS18 have different options for slew rate and drive strength. For example, LVCMOS33 offers seven different drive strengths, while LVCMOS only offers four.

It's not unreasonable that the actual circuitry that configures these ancillary features is sensitive to the voltage provided on VCCIO. For example, if an output driver configured to drive 4 mA expecting 3.3V on VCCIO only gets 1.8 V on VCCIO, it could fail to drive the pin at all, drive an unexpectedly low current, or drive the normal current but fail to swing far enough. To know the exact behavior we would likely need to know the implementation details of the IOB, so it's best to just follow the datasheet requirements.


Setting the IO standard more todo with what said standard implies/supports rather than just the voltage.

The FPGA cannot change via synthesis the output voltage nor the input thresholds as that in controlled by what a bank is power from. It however does permit configuring the drive strength and the slew rate aligning to certain LVCMOS standard. This is key when matching impedances.



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