Need help shrinking a 4-bit binary Adder/Subtractor/Multiplier calculator circuit

Question

Project Description: A mini-calculator that performs addition, subtraction, and multiplication on two 4-bit inputs (0-9) and displays the inputs and resulting numbers in 7 segment displays. Aside from the two 4-bit inputs, there is also a 2-bit input to decide which arithmetic operation is used. 00 is off, 01 is addition, 10 is subtraction, and 11 is multiplication. I am only allowed to use AND, OR, XNOR, NOR, and NOT gates. Absolutely no other gates or IC's. I am to implement the project on a breadboard.

This is my current design (I adapted the binary to BCD circuit from the design of Jonk ), already tested the whole circuit and it works perfectly.

Adder/Subtractor - Uses the standard full adder circuit. I attached it into a 2's complement circuit which basically inverts the input and adds 1 to it. This is for the negative difference during subtraction, which also turns on the left bottom 7 segment's g, displaying - sign.

Multiplier - Again, using the standard full adder design. The maximum output is 81 (9x9), a 7-bit binary number.

The miscellaneous gates between the adder/subtractor and multiplier ensures that only the result of the correct circuit on the corresponding 2-bit input will be passed on to the binary to BCD converter. Others in the middle of the circuit is a combinational circuit that drives 3x3 LEDs to display +, -, and x, and two rows of LEDs for the equals sign. The four combinational circuits at the right are the BCD to 7 segment decoders.

The outputs of the adder/subtractor and multiplier are fed to the binary to BCD converter, since their maximum values are 18 and 81, respectively, so I need to convert these more-than-4 bits numbers into BCD to drive them into the 7 segments decoder.

The outputs are two 7 segments at the top displaying the inputs, and a 3x3 LED for the operation (e.g. 9+7). The first 7 segment at the bottom is for the negative sign, and the second and third bottom 7 segments are for the resulting number.

However, as seen from the picture, it uses too much logic gates. I calculated and estimated it to require more than 90 ICs, and probably around 18 long breadboards, which will be a nightmare to wire.

Is there any other way to simplify the circuit? Or any other circuit that can replace one of the blocks in the whole circuit? I'm aiming for 60+ ICs, preferably 50+. I do think that I could find a way to design a simpler binary to BCD, but the only ways I could find were the double dabble algorithm and converting binary to decimal then to BCD.

Answer 1

My approach to this kind of problem is to start at the basics, which make sense, and then optimize.

Multipler

A basic multiplier starts with generating the partial products. That's just a bunch of AND gates. Then it follows this up by adding up the partial products. So that is just a standard adder configuration.

Here's an example that shows the standard adder of partial products, but also includes the Wallace tree version:

Note that the number of full adders and half adders is the same for 4 bits. The difference is in the worst-case delay.

However, given that you are only dealing with BCD digits and not the full range of unsigned binary values, the Wallace tree can be reduced to:

That takes some advantage of the fact that we are only dealing with BCD as inputs.

Add/Sub

You already pretty much know about the adder/subtractor. That much I can see. The only addition needed, because you want to display the results with 7-segment displays, is that instead of a twos-complement output you really need a signed-binary output, instead.

I suspect this could be simplified still further, but the obvious approach is to stick with the usual add/sub approach and then follow it with a complement and add-1 conversion if the result is negative.

I did it this way:

Nothing terribly obscure there. Just the usual twos-complement approach on the left, followed by some logic to convert a twos-complement negative result into a signed-binary output.

MUX

At this point, you need some way of selecting either the add/sub output or else the multiplier output. In the case of the multiplier, the result is always positive. The sign is negative only when subtraction is selected. And then, only sometimes.

The mux arrangement I used combines the above as follows:

Display

You already found my earlier writing about the double-dabble algorithm and the digital implementation.

I did a little bit of enhancement to it (optimized it) because of the maximum binary output of 81 (from 9 times 9.) This allowed some reductions as shown:

The conversion of BCD to 7-segment display looks like this:

You already know what the logic looks like for the SADD3 sections (you cited my work in your question.) So I won't repeat it here.

That's about it.

Final

The final result is here:

This requires:

(10) INV     (2) 7406, +2
(73) AND    (19) 7408, +3
(44) OR     (11) 7432, +0
(12) NOR     (3) 7402, +0
(53) XOR    (14) 7486, +3
--------------------------
191         (49)

(If you use one INV and one NOR to create one OR gate to save one 7432 IC, that way.)

This is 49 ICs!! Not bad. Considering you don't get to use a 7483!