Divided vs Multiplied clock

Question

I heard someone saying that for example for FPGA design, it is better to multiply the input clock in the PLL and then use the result as my main clock instead of divide my clock in the PLL, for reasons of jitter/ or some reason I dont remember.

For the sake of the question, lets assume you are FPGA engineer and you should work with internal clock of 100MHz inside the FPGA, would you prefer the Board designer will provide you external clock source of 50MHz or 200MHz?

this system:

or this:

If some of the option is better than the other, what is the explanation for this?
I beleive that using external clock of 100MHz and using the PLL as a buffer to pass the same clock frequency is the best option, what is the reason for it?

Thanks!

Answer 1

Remember that a PLL is just a self-adjusting variable oscillator, where the adjustment is done by comparing the phase of the input oscillation with that of the oscillator, and then feeding back a filtered difference signal.

A PLL can hence be used to clean up a jittering slower clock while upconverting – simply by having a more stable variable oscillator, and making that loop filter bandwidth narrow enough to "average out" the jitter.
Of course, a PLL itself has noise, so you're also adding some of your own jitter.

But: typically, the low-frequency reference clocks are the best clocks in a system. So, the PLL then only makes phase noise worse – not something you want.

So, assuming both your 50 MHz and 200 MHz clocks are good (as in: lower-noise than what the VCO of the PLL can produce on its own), then going 50 MHz -> PLL -> 100 MHz is going to have more noise. That's because for going from 200 MHz to 100 MHz, you wouldn't use a PLL at all, you'd just use a 2-bit counter (and use the upper bit of that as output). Then you get the same jitter standard deviation at the output as on the input!

If your clocks are equally bad in terms of jitter / phase noise, well, then it really makes no difference, either. You would use a PLL with a good VCO in both cases, and what defines the output phase noise / jitter is the loop bandwidth of that PLL - and that could be the same in both cases.

So maybe there's more practical reasons to what you've been told - maybe the 200 MHz oscillators they have are worse than their 50 MHz oscillators? Or maybe they are running out of PCB space and hence can't run a differential clock line to the FPGA, which is no big deal at 50 MHz, but might become more complicated at 200 MHz (this would be a bit surprising, if you're layouting an FPGA board, a 200 MHz clock, especially of the harmonic oscillation kind, certainly isn't the most challenging part of your layout)?

Answer 2

Timing clock signals, of the majority of electronic products are generated by quartz crystal oscillators or Silicon oscillators. Some are temperature controlled to keep the signal stable in time, many aren't.

Quartz crystal oscillators or Silicon oscillators are designed to generate clock signals in in the (10 KHz, 100 MHz) range, where costs increase with frequency.

It's not trivial going beyond 100 MHz.

Decent FPGA's can work well up to 1 GHz.

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To answer your question:

The problem here is how to multiply a base frequency up to 1 GHz and not to scale it down.

Scaling down frequencies is pretty easy using 74HCXXXX counters.