I come from analog/RF background and have limited knowledge in digital interfaces. According to TI's articles about Ethernet PHY found here and here, single MAC to single PHY connection seems very straight forward. You have xMII and MDIO/MDC connecting one MAC to one PHY.

Where I get confused is when an Ethernet switch IC comes into play. I have a circuit that uses 88E6320 as an Ethernet switch IC and has a block diagram like below (sorry, can't upload schematic and datasheet) enter image description here

  • Ports 3 and 4 are 10/100/1000 transceivers.
  • Ports 2 and 6 are configured as RMII PHY mode using strapping resistors.
  • Ports 0 and 1 are SGMII, connected to a soft fabric of FPGA w/ integrated MAC.
  • Port 5 is configured as RGMII using strapping resistors, connected to a hard fabric of FPGA w/ integrated MAC.

What I don't understand is

  1. Isn't xMII used to connect PHY to MAC? How can ports 2 and 6, configured as PHY mode, still talk to external PHYs?
  2. Any reason to connect two PHYs back to back (like port 2 and 6 to external PHY) using xMII? Or in other words, why not set ports 2 and 6 in MAC mode if they are interfacing with external PHYs?
  3. Datasheet for the switch doesn't say anything about port 1 (SGMII) and port 5 (RGMII)'s MAC/PHY mode. How can I know which mode port 1 and 5 are operating in?


  • \$\begingroup\$ Hey,,, yah.. I may try to explain, guessing, though not sure, So the left most side accesses the Marvell's registers either through port 1 or port 2 (MDIO & MDC), including the PHY registers in Marvell for port 3&4, then external PHY-s through RMII of PORT 2&6 of Marvell (MDIO & MDC pass through). Now, Marvell (guessing, without reading datasheet) work as a Ethernet switch. About port #6 connection, It is just used in that way for it is convenient to use all the software stack built over Ethernet, and communicate between the leftmost and the right most. So, again that is all I guess. \$\endgroup\$
    – jay
    Commented Nov 8, 2021 at 23:48

1 Answer 1



for port 2 and 6, the phy is external. Unfortunately though not all phy information is present on an RGMII/GMII and this is sent over MDIO/MDC. The switch needs to know you have a phy connected, and hence that mode.

It's possible to connect RGMII/GMII to another mac also and skip the phy.

2/ there is no internal phy if it comes out RGMII/GMII, and if you are going from mac to mac there will not be a phy

3/ when you mean mode here - I assume you mean which speed for SGMII this is encoded in the negotiation in the 8/10 stream

if you mean mac/phy mode instead for a port - I'm not sure but take a look at where in your switch you assign the phy MDIO address and there should be a clue there as to why it is needed or not I don't happen to have the marvell data sheet at the moment

most switches of this era and speed genre poll the PHY's over MDIO to get link/speed info


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