I made a 4x multiplier on the switch node of a boost circuit.

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I don't quite understand how DC pulses behave in a voltage multiplier.

  • C1, C2, C4, and C10 don't seem to contribute to series discharge.
  • Why is the half stage needed? (D1 and C11.)
  • Will more current flow through D1 than rest of the diodes if x4 node is driving the load?
  • What is the voltage in some nodes? (see global tag.)
  • If I want to attach a load to some of the nodes other than the x4 node, can I add a bulk capacitor between the node and ground without disrupting the voltage multiplier?
  • Why is the end node x4 instead of x5? C11-C15 will series discharge.
  • \$\begingroup\$ Why not use a simulation tool? Why not dispense with all the voltage doubling and directly regulate at 114 volts using the inductor as intended? It seems you are over-complicating what is a basic and simple circuit. To what ends? \$\endgroup\$
    – Andy aka
    Nov 9, 2021 at 12:29
  • \$\begingroup\$ @Andyaka I want duel supply boost 5-12V to 200V and 500V. Most PMICs do not operate at those extreme duty cycle. This SMPS needs to be very compact, so I rejected flyback (too many components and you have to wind the transformer yourself for desired ratio). \$\endgroup\$
    – 7E10FC9A
    Nov 9, 2021 at 12:39
  • \$\begingroup\$ In DCM from 5 volts to 500 volts it would be about 80% duty cycle (load dependent of course). \$\endgroup\$
    – Andy aka
    Nov 9, 2021 at 12:50
  • \$\begingroup\$ About your 5th question: The point marked with VOUTx4 is where the main output (i.e. the one to be regulated by the controller chip) is taken from. So it's already has its own bulk capacitor. \$\endgroup\$ Nov 9, 2021 at 12:57
  • 1
    \$\begingroup\$ I'm not sure "too many components" is a valid reason to go with this over flyback, considering how many diodes and capacitors you've added here. \$\endgroup\$
    – Hearth
    Nov 9, 2021 at 16:32

2 Answers 2


Your design is not feasible.

Here is a much better compromise with fewer boost stages and only using 1 polarity in this 2005 IEEE paper: A Boost Converter With Voltage Multiplier Cells

N=2 is feasible for 200W.

enter image description here

Theory of (poor) operation

The main issue is the long series Cap strings are low ESR and the FET on transition with low RdsOn needed injects a very large \$Ic=C dV/dt +Ic*ESR\$ for a short T duration.

However, it can be improved greatly with a series LC filter with a 1:1 L ratio in series with the boost outputin order to attenuate the very large current spikes into the string of low ESR 1uF ceramic caps.

This cascaded voltage multiplier starts with a very low RdsOn NFET with a boost regulator. The current spikes are huge as the power is transferred on the edges of in half cycle of full wave rectifiers. The 1st lower Cap rectifies the larges positive edges current and power while the 1st upper Cap rectifies the negative edge at half the current, considering the ESR's of both Caps are in series.

However, if the source impedance is not < 10 mohm, conversion voltage ratio suffers greatly, even with no load due to dV/dI to ESR ratio.

Current spikes gradually increase overall as the voltage rises until decaying to steady state multiple Vdc of the number of full bridge stages or 4.5 in this case with no load. As with all transformed voltages the output impedance becomes the square of the voltage ratio multiplied by the DCR+Ron + the cumulative ESR sum of each full bridge ESR (including diodes)

Each parameter of Pmax has a low duty cycle dependent on the crest factor and the Q of each reactive component. This also can be correlated by the ratio of the Time Constants T * 1/f or the ratio of the inverse time constants =1/(ESR * C) which are >=1e7 for ceramic and <= 1e6 for e-caps and for the inductor DCR/L might range from 0.1 to 1000 with DCR's near the RdsOn value and ESR value as a starting point that is load dependent for L/C ratios as the 1st stage Drain with switch off \$Z_{ds}=\sqrt{\frac{L}{C_{in}}}\$.

There is no reason for asymmetrical caps which could be 5+5.

With 1mohm FET and 10mohm ESR 1uF (T=1e-8) caps , the caps might see 1kW spikes which create massive EMI. The diodes with the lowest leakage and lowest Vf at 10A might not be the Schottky diodes you imagine, rather >=1A Si diodes might be best.

Since the power factor is so poor, a CCM boost 3ϕ regulator would provide lower output/load impedance ratio or namely, load regulation with low source ripple, and easier selection of passives.


Don't use my components names! See only OP names. NB : behavior is quasi "the same" when all lower capacitors return to ground.

For reference : external behavior of voltage "multiplier".


Q1: "C11, C12, C13, C14, C15. (OP schematic, lower capacitors) These capacitors are return of DC component voltage. The voltages are "constant" and are "lower" when going to the right. Voltages of points to ground are "greater" going to the right.

enter image description here

The other capacitors C1, C2, C4, C10 transmit the pulses to every 2 diodes. The voltage on capacitors" is a "pulsing" voltage that is quasi the same for all capacitors. (OP schematic, upper capacitors)

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Her is at start and with inductor 110 uH, Rserial = 1u Ohm.

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And the other

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  • \$\begingroup\$ Sounds nice but incorrect. These caps store charge from positive rectifiers and negative clamp rectifiers on alternate edges All the upper caps charge synchronously with a short triangular power spikes on the input negative edge and visa versa for the lower caps. when the FET closes. These form series voltage loops in between. for the spike power increases on each cycle until approaching steady state. \$\endgroup\$ Nov 9, 2021 at 18:39
  • \$\begingroup\$ plot the cap power V*I to verify my assertion for the 1st say 20 cycles. Why are you choosing a massive L1 with DCR/L=1s^-1 try 100:1 or more for practical solution which implies at 10kHz you need a much lower L. This choke media.digikey.com/Photos/Hammond%20Mfg%20Photos/MFG_195B150.jpg is 1mH 3 mohm or DCR/L=3 . Digikey doesn't sell any =1 \$\endgroup\$ Nov 9, 2021 at 18:55
  • \$\begingroup\$ Ok... Will lower L to 100 uH. Note that transients at start are not beautiful without a "soft start" duty cycle. \$\endgroup\$
    – Antonio51
    Nov 9, 2021 at 19:16
  • \$\begingroup\$ Use a realistic DCR/L ratio \$\endgroup\$ Nov 9, 2021 at 19:17
  • \$\begingroup\$ It would be, perhaps, "better" to use a sinusoidal generator for understanding ? \$\endgroup\$
    – Antonio51
    Nov 9, 2021 at 19:36

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