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I am designing a board with a Spartan 3E. I have chosen linear voltage regulators for powering the FPGA which should be well suited for this chip.

I am now routing the board and I am wondering if anyone could comment on the power planes. I have some experience in digital electronics but few in power electronics.

The star in the middle is 1v2, the square around the star is 2v5 and the rest is 3v3.

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    \$\begingroup\$ It would be very highly adviced to route the 1v2 and 2v5 on different layers. In your current layout, the 2v5 has to go through 3 choke points and around a large loop to reach the pins to the right. Both of that increases the supply impedance quite substantially. Ideally, you have extended planes for each of the supplies (layer count permitting) and only run vias to the pins. \$\endgroup\$
    – tobalt
    Nov 9, 2021 at 12:29
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    \$\begingroup\$ Use a 4 layer board. \$\endgroup\$
    – Andy aka
    Nov 9, 2021 at 12:32
  • \$\begingroup\$ I understand. This is a 4 layer board so that's why I went with this. \$\endgroup\$ Nov 9, 2021 at 12:33
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    \$\begingroup\$ Well I guess multi-supply-rail IO monsters like FPGA are where 4 layer boards are at their limits. \$\endgroup\$
    – tobalt
    Nov 9, 2021 at 12:36
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    \$\begingroup\$ 6-layer boards aren't as exotic/costly as they perhaps used to be. Weigh that against the additional cost of EMC struggles, or an FPGA design that closes timing in the sim, but then doesn't work as expected. \$\endgroup\$
    – tobalt
    Nov 9, 2021 at 13:05

1 Answer 1

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I'd check the requirements of the various planes, that should tell you what is important.

Without having read the datasheet, my expectation would be

  • 1.2V is VCCint, the supply for the logic itself. This will require lots of decoupling and low impedance connections, because this is where the majority of the power draw is on, and where the power draw is the least stable.
  • GND is the return for all the supplies including VCCint, so the same worst-case requirements apply.
  • Some of the 1.2V and 2.5V might be supplying a PLL. These should be very stable, but draw little power. It may make sense to route these as traces, and use a linear regulator from the next higher rail, or derive them with an LC filter.
  • The 3.3V are VCCio, and these are organized in independent banks. Power draw depends mostly on switching speed and whatever other components are there, so from a noise and current POV it's in the middle between VCCint and the analog supply for the PLLs. The currents you'll see on those is the sum of the currents on the IO pins, so the absolute maximum is the combined drive strength of all pins in a bank.

For such a scenario, I'd use the two inner layers as 1.2V and GND and connect these first, then try to connect as much as possible on the top layer (to avoid creating more holes than necessary). It's likely that you will have to run signal traces between the two pads of a decoupling capacitor. I'd only place one ring of decoupling caps next to the IC, and share the higher capacitances between multiple pins.

The 2.5V pads should be near the PLLs. Altera places these in the corners, I believe Xilinx does that as well, so

The 3.3V can be run alongside the signal traces on the top, or on the bottom under the FPGA. It is okay to route each bank separately as well, that way you need no connections through the middle of the FPGA, and you can place the PLL supply from the middle outward to the corners, and the IO supplies coming in from the side.

Of course, all of that goes out of the window if you have a bottom pad that needs a good thermal connection to a plane on the bottom.

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    \$\begingroup\$ "I'd use the two inner layers as 1.2V and GND" I would like to suggest that this only applies for a stackup where L2 is tightly spaced to L3. Otherwise the 1.2V power plane will just couple to anything on the outer layers and create a lot of EMI, integrity problems. Most 4-layer stackups I have seen have a 1mm gap betwenn L2 and L3 and will lead exactly to this terrible scenario. But I guess realizing this well in a 4-layer board would anyway require some special stackup which will end up more expensive than a default 6-layer stackup with 3 tightly spaced pairs. \$\endgroup\$
    – tobalt
    Nov 9, 2021 at 14:04
  • \$\begingroup\$ @tobalt, hmm, might more sense to use L2 as GND and L3 as 1.2V if the signals are on L1, and that should also resolve the concern about the distance between L2 and L3. \$\endgroup\$ Nov 9, 2021 at 15:03
  • \$\begingroup\$ If L3 and L4 are tightly spaced, then 1.2V on L3 will couple that to everything on L4 and little to the L2 GND plane. You generally should tightly couple those high speed power distribution planes to GND planes. This is (in my point of view) the dilemma with the 4 layer board: You can't use large power planes because the power has to be on the same layer as the signals (because you need power+GND tightly spaced and also signals+return tightly spaced). But then again, I guess many people have passed EMI with 4-layer FPGA designs without tightly spaced power+GND. \$\endgroup\$
    – tobalt
    Nov 9, 2021 at 15:13
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    \$\begingroup\$ @tobalt, yes, I doubt EMI will be much of an issue here. This is a Spartan3 in a QFP package after all, that will likely max out at 150-ish MHz and there are decoupling caps on the top side between the vias to the power plane and the power pins. The biggest issue this board will have is keeping the digital noise out of the PLL power. Out of sheer laziness I'd probably give each PLL its own filter right next to the pins, but I'm biased because I still have a reel of 1uH inductors lying around. \$\endgroup\$ Nov 9, 2021 at 16:37
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    \$\begingroup\$ With six layers, I'd probably go signal-GND-1.2V-3.3V-GND-signal, and generate the 2.5V near the IC with a linear regulator. In my opinion, since this isn't a demanding design, I think it's not worth going to six layers unless the cost difference is really small. \$\endgroup\$ Nov 10, 2021 at 9:37

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