I'd check the requirements of the various planes, that should tell you what is important.
Without having read the datasheet, my expectation would be
- 1.2V is VCCint, the supply for the logic itself. This will require lots of decoupling and low impedance connections, because this is where the majority of the power draw is on, and where the power draw is the least stable.
- GND is the return for all the supplies including VCCint, so the same worst-case requirements apply.
- Some of the 1.2V and 2.5V might be supplying a PLL. These should be very stable, but draw little power. It may make sense to route these as traces, and use a linear regulator from the next higher rail, or derive them with an LC filter.
- The 3.3V are VCCio, and these are organized in independent banks. Power draw depends mostly on switching speed and whatever other components are there, so from a noise and current POV it's in the middle between VCCint and the analog supply for the PLLs. The currents you'll see on those is the sum of the currents on the IO pins, so the absolute maximum is the combined drive strength of all pins in a bank.
For such a scenario, I'd use the two inner layers as 1.2V and GND and connect these first, then try to connect as much as possible on the top layer (to avoid creating more holes than necessary). It's likely that you will have to run signal traces between the two pads of a decoupling capacitor. I'd only place one ring of decoupling caps next to the IC, and share the higher capacitances between multiple pins.
The 2.5V pads should be near the PLLs. Altera places these in the corners, I believe Xilinx does that as well, so
The 3.3V can be run alongside the signal traces on the top, or on the bottom under the FPGA. It is okay to route each bank separately as well, that way you need no connections through the middle of the FPGA, and you can place the PLL supply from the middle outward to the corners, and the IO supplies coming in from the side.
Of course, all of that goes out of the window if you have a bottom pad that needs a good thermal connection to a plane on the bottom.