I'm trying to implement an SPI device in Verilog. I'm having a lot of problems for coordinating master and slave, since sometimes (with my current impl.) the SPI master device doesn't send enough clock pulses to the slave so it can finish its processing.
For instance, this can occur if the slave is implemented so that its state machine has more states, and it stops receiving clock pulses before it finishes completing its cycle.
I could modify my implementation to make these two devices to be coordinated in terms of clock pulses, however, this means that the master implementer needs to know the impl. details of the slave (and all the potential slaves). This doesn't seem right to me at all.
Does the SPI protocol specify exactly how many pulses the master must provide to the slave when sending, for instance, one byte? If not, how is that any SPI master device is compatible with any slave? Would it be ok to send a ton of pulses (e.g.: 64 pulses for 1 byte) to the slave just in case?