I am working on a design with a Cyclone-V FPGA.

  • I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother.
  • 4 DFFs running on each of these respective clocks. The outputs of these 4 DFFs are connected to a 4:1 mux.
  • I would like the outputs of the 4 DFFs going into the mux to have equal path delay (or equivalently path delay to the output of the mux).
  • The output of this mux is a clock connected to a global clock buffer.
  • The mux selects only switch when all 4 mux inputs are low and will be low for a long time. Therefore, we are not concerned with constraining the mux select path.
  • All of the circuitry is internal to the FPGA (no I/O)

The clocks are defined here:

create_clock -name {CLK_250_IN_g[0]} -period 4.000 -waveform { 0.000 2.000 } [get_pins { inst_pllgclkbuff4_cve_CLK_250_IN|inst_cycloneve_clkctrl[0].inst_cyclonev_clkena0|outclk }]
create_clock -name {CLK_250_IN_g[1]} -period 4.000 -waveform { 1.000 3.000 } [get_pins { inst_pllgclkbuff4_cve_CLK_250_IN|inst_cycloneve_clkctrl[1].inst_cyclonev_clkena0|outclk }]
create_clock -name {CLK_250_IN_g[2]} -period 4.000 -waveform { 2.000 4.000 } [get_pins { inst_pllgclkbuff4_cve_CLK_250_IN|inst_cycloneve_clkctrl[2].inst_cyclonev_clkena0|outclk }]
create_clock -name {CLK_250_IN_g[3]} -period 4.000 -waveform { 3.000 5.000 } [get_pins { inst_pllgclkbuff4_cve_CLK_250_IN|inst_cycloneve_clkctrl[3].inst_cyclonev_clkena0|outclk }]


I attempted to achieve this by constraining this path with set_max_delay and set_min_delay in my sdc (there are 4 copies of these constraints for each of the 4 registers).

set_max_delay -from [get_cells {inst_clkgen_a|inst_clkgen_phases|CLKOUT_phases[0]}] -to [get_cells {inst_clkgen_a|inst_mux4_1_CLK_OUT|Mux0}] 0.100
set_max_delay -from [get_cells {inst_clkgen_a|inst_clkgen_phases|CLKOUT_phases[1]}] -to [get_cells {inst_clkgen_a|inst_mux4_1_CLK_OUT|Mux0}] 0.100

set_min_delay -from [get_cells {inst_clkgen_a|inst_clkgen_phases|CLKOUT_phases[0]}] -to [get_cells {inst_clkgen_a|inst_mux4_1_CLK_OUT|Mux0}] 0.000
set_min_delay -from [get_cells {inst_clkgen_a|inst_clkgen_phases|CLKOUT_phases[1]}] -to [get_cells {inst_clkgen_a|inst_mux4_1_CLK_OUT|Mux0}] 0.000

This is making no difference to the path delay from the Q output to mux.out. The resulting path delays are shown in the circuit diagram, indicating the min/max constraints are not working.

How is possible to accomplish this?

  • \$\begingroup\$ Yah, it is difficult to put delay under ... manipulation (control sounds a bit far from what we are trying). Sometimes, people play with .. let me recall.. CELL or LCELL(?) selection or placement. IIRC, there was some version of PLD with something like delay-line element, I might be too wishful. \$\endgroup\$
    – jay
    Nov 9, 2021 at 17:41
  • \$\begingroup\$ Jay, thanks. Will look into that. I saw another post here using delay lines, so I can give that a shot. \$\endgroup\$
    – cplusruss
    Nov 9, 2021 at 20:49

2 Answers 2


Your clock constraints look fine. Your delay constraints look fine as well.

min/max constraints are not working

That's not what you should interpret from the Timing Analyser's report. You asked for \$0.1 \text{ ns}\$ max path delay, which looks unrealistic for the Timing Analyser to achieve on that path on a Cyclone-V FPGA. Around \$1 \text{ ns}\$ is the best it could come up with. In other words, your design has failed to achieve the timing requirements specified by you. Not that the constraints are wrong.

I would like the outputs of the 4 DFFs going into the mux to have equal path delay

You should not worry about getting exact path delays, as it doesn't make much sense on timing paths on a clocked synchronous design. And no Timing Analyser and Synthesiser can place and route at the exact path delays as the user wishes. You can specify only a range within which the delay should be constrained to: (min , max). Synthesiser will attempt to route your design accordingly, meeting setup and hold requirements as derived from the (min, max) constraints.

  • \$\begingroup\$ Mitu, fantastic. Thanks so much. I sort of had a hunch that the min/max was too much, but wasn't seeing any violation in the report. Will try with some bigger numbers -- like min 4 nsec, max 4.2 nsec or something like that. \$\endgroup\$
    – cplusruss
    Nov 9, 2021 at 20:29
  • \$\begingroup\$ Mitu, this design is not synchronous (no registers on the output of the mux) -- do you know if the set_min_delay actually adds routing delay? \$\endgroup\$
    – cplusruss
    Nov 9, 2021 at 20:45
  • 1
    \$\begingroup\$ FPGAs are used for synchronous designs and you have clock in your design. The path you talk about may or may not be synchronous. It depends on where this signal is actually going to. Maybe it's going to another flop sitting inside/outside the FPGA which is driven by the same or another synchronous clock? In that case, it is synchronous reg-to-reg path. You have not provided that information though. \$\endgroup\$
    – Mitu Raj
    Nov 9, 2021 at 20:52
  • \$\begingroup\$ set_min_delay will only convey the minimum delay you target on that path. The Timing Analyser tries to achieve it during synthesis and place and route and finally computes the actual logic + routing delay on that path, and then reports the slack. ie., the difference between your requirement and the actual delay. \$\endgroup\$
    – Mitu Raj
    Nov 9, 2021 at 20:56
  • \$\begingroup\$ Thanks Mitu. Yes, that's true. Technically speaking, the output of this mux goes to a pin. I might want to constrain to that. \$\endgroup\$
    – cplusruss
    Nov 9, 2021 at 21:10

Set max skew constraint in your SDC file. Here is a link that shows the command.


The example below sets the max skew to 0.2 ns.

set_max_skew -from [get_registers {CLKOUT_phases[0] CLKOUT_phases[1] CLKOUT_phases[2] CLKOUT_phases[3]}] -to [get_ports {CLK_OUT}] 0.2 

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