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I've noticed that in most designs synchronized signals crossing clock domains are implemented for control signals.

I'm, however, wondering what the criteria is to add synchronization to the data bus as well.

Would that depend on the ratio of the destination clock vs source clock? Or is it more closely associated to the number of bits to be passed between domains?

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If the data path uses a FIFO, as long as the pointers don’t cross the write and read paths have no asynchronous path. They're considered to be in separate clock domains. (The FIFO could even be a one- or two-level register depending on how the two sides handshake with each other.)

The managing of this pointer-cross business is dealt with by the control path, which if properly designed will ensure that the pointer-cross corner case never occurs.

An issue that comes up frequently relates to the clock ratios of read vs. write. If read clock is significantly slower, this adds turn-around latency to the write-read handshake. This comes up as the FIFO approaches full: the read pointer in the slow clock domain will take a long time to change state, delaying the FULL calculation. If the write side doesn't see this in time it can overrun the FIFO. The answer to this case is to give an earlier almost-full to the write side, so that any extra writes can still make it to the FIFO. This is called a skid buffer.

Related: what is the specific reason for using FIFO in asynchronous domain at VLSI?

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  • \$\begingroup\$ thanks for the detailed reply! How would the scenario you're describing be laid out if there is not FIFO present? \$\endgroup\$
    – nanoeng
    Nov 10 '21 at 0:26
  • \$\begingroup\$ The control handshake would have to ensure stable data until the read side has accepted and acknowledged it, using a fully interlocking handshake. The inter-domain connection for data would then be treated as a false path for STA. Older computer buses were like this (68000, ISA Bus, etc.) \$\endgroup\$ Nov 10 '21 at 0:32

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