In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper clock-domain crossing?
At the moment, I'm assuming the calculation for the number of stages should go something like this
200/30 = 6.67
As such, I'd need 7 flip-flop stages to be able to meet the clock-domain crossing requirement. Is this a correct assumption?
The system has multiple control signals and a couple of data-buses going back and forth. The widest bus is 32-bits while the smallest bus is 24-bits.