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I am designing an FMCW radar, for which I need to generate an RF signal ramped in frequency. To accomplish this, I want to use a direct digital synthesizer (DDS) to generate the ramp at baseband then upconvert it to RF.

For the upconversion, I thought I wanted to use a phase-locked loop (PLL) to generate the RF frequency then mix it with the output from the DDS.

All of the PLLs I see that work with my design (e.g. ADF41020) have \$ RF_{IN} \$ pins, however. I have never seen this and am confused on its operation.

Does the signal input to \$ RF_{IN} \$ get converted to the PLL's configured frequency? Can someone explain what is generated?

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The PLL chip that you have selected includes dividers + a phase detector, but not a VCO. From the datasheet:

A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO).

In a full PLL realization, you will connect the CP output of the ADF41020 to the loop filter and VCO; the VCO will generate an RF carrier, which can be delivered to:

  • The mixer, for upconversion by mixing with your DDS output.
  • Back to the RF pin, as feedback for the PLL. The ADF41020 will track the relative phase of the RF input and the reference clock (divided as appropriate) to maintain the desired RF ouptut frequency as a product of the reference clock and the configuration of its onboard clock dividers.

The same vendor also offers PLLs with integrated VCOs, for example this one. To use it, you would attach your own loop filter between CPOUT and VTUNE, and it will internally provide feedback from the VCO back to the PLL.

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