I have almost finished a project that was supposed to output a square wave signal with a certain frequency but when I tried to make a small change to the circuit something weird happened to my output.

Here is the circuit with +-5 V power supplies:

enter image description here

enter image description here

As you can see at the very end of each pulse a small distortion appears when I am using a Zener diode as a reference.

Before I was using a transistor that functioned as a diode and my output was still not perfect, but better.

Why does the output spike like this when I change the reference to a diode and also changed the values of the bias resistors? A better question, how can I minimize these spikes overall?

P.S I've tried playing with the Miller capacitor but 47pF was the sweet spot.

  • \$\begingroup\$ First thing, you need some amount of cap, shunt with R1 (Rl ?). Peaking is larger, because Zener V > tranZistor V.... guessing.. \$\endgroup\$
    – jay
    Nov 10, 2021 at 20:55
  • \$\begingroup\$ I like the "certain frequency" and the nicely cut-off time stamps by which we might observe through your (intentionally? I'm guessing) obscure writing about it. When considering the idea of such spikes, the first step in considering sources is to know something about the time constants, which you've left out. We could guess. But this is key info, I think. Could you consider opening your hand here and let us know the timing periods involved? \$\endgroup\$
    – jonk
    Nov 10, 2021 at 23:06
  • \$\begingroup\$ I wanted to know in general why this spikes happend, but my cerain frequency is any in the [15,45] kHz range. \$\endgroup\$
    – PowerTb321
    Nov 11, 2021 at 7:25

1 Answer 1


It appears to me that when the output is in the low state, Q10 is switched off and so the current for the collector (and emitter) of Q7 needs to come from the base of Q8. Q8 base can't supply enough base current to keep the Q7 current source happy and so instead, the Q7 current source pulls the required current through its base from the zener regulator.

The zener regulator can't supply this extra current and so its voltage drops.

I would try reducing R18 to say 1k and see if that helps.

(In your diagram, the zener doesn't appear to be connected to the bases of the current sources)

  • \$\begingroup\$ Well it did help, thank you for your answer. But now I have another question, how do I choose the valules for R3 and R9? For example I picked R3 to be 1k and so I have an Itail for about 2mA which is pretty good for the diff pair. But for R9 for example, if I play with it's R ( in a range between 100 and 1k ohm) I still get some nonlinarity ( and sometimes really small spikes). The value of 820 ohm for R9 seems to work the best, but can't figure out why. Thank you again for your answer! \$\endgroup\$
    – PowerTb321
    Nov 11, 2021 at 7:42
  • \$\begingroup\$ @PowerTb321 If you have too low a value for R9 then you are back to the original problem, the base of Q7 will draw more current from the zener regulator than it can supply without dropping its voltage. If you lower R9 then you will have to also lower R18 further. If R9 has too high a value then you are lowering the current available to drive the output. I can't see what your load resistor value is but if you increase R9 too far then you will have to increase your load resistance to compensate. The total load comprises of R7, R8, R17, R10 and that resistance that is just out of view. \$\endgroup\$
    – user173271
    Nov 11, 2021 at 8:55
  • \$\begingroup\$ My Rl is 15k ohm and I understand your point. My problem now is that when I measure the phase margin for my circuit is really not that good. Or maybe I don't understand how to measure it for my case becouse 0dB is at around 5MHz(which is way higher than my frequnecy interval) with a value for pahse margin of 10 - 15, wtich bothers me. How can I make my circuit stable overall? ( P.S increasing the Miller capactior works, but my signal get's really distorted) \$\endgroup\$
    – PowerTb321
    Nov 11, 2021 at 10:17
  • \$\begingroup\$ @PowerTB321 Reducing the tail current in the input stage will reduce the transconductance of the input stage thereby reducing open loop gain and loop gain which will increase stability margins (phase and gain margins). Increasing the size of the compensation capacitor will also improve stability margins by reducing the transresistance of the second stage which is equal to the reactance of the compensation capacitor but you say this causes problems. Problem is, reducing the tail current will slow down the output square wave edges and so it is a trade off between slew-rate and stability. \$\endgroup\$
    – user173271
    Nov 11, 2021 at 11:05
  • 1
    \$\begingroup\$ @PowerTB321 The other factor which affects stability margins is the amount of feedback. That circuit has both +ve and -ve feedback. To improve stability, reduce the amount of negative feedback (increase R17 or increase C1 which reduces the feedback fraction (beta)). Alternatively you could try reducing the amount of +ve feedback by increasing R7 or reducing R8. I haven't actually tried the latter before so it would be a bit of an experiment - but it makes sense in theory. Note that as you vary R17, the stability margins will vary. \$\endgroup\$
    – user173271
    Nov 11, 2021 at 11:21

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.