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I am designing "0110" overlapping sequence detector using moore model in verilog

verilog code:

`timescale 1ns / 1ps

module seq_detector(
input x,clk,reset,
output reg z
);

parameter S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 , S4 = 4;
reg [3:0] PS,NS ;

    always@(posedge clk or posedge reset)
        begin
            if(reset)
                PS <= S0;   
            else    
                PS <= NS ;
        end             

    always@(PS or x)
        begin 
            
            case(PS)
                S0 : begin 
                            z <= 0 ;
                            NS <= x ? S0 : S1 ;
                            $display(PS);
                        end
                S1 : begin 
                            z <= 0 ;
                            NS <= x ? S2 : S1 ;
                            $display(PS);
                        end
                S2 : begin 
                            z <= 0 ;
                            NS <= x ? S3 : S1 ;
                            $display(PS);
                        end 
                S3 : begin 
                            z <= 0;
                            NS <= x ? S0 : S4 ;
                            $display(PS);
                        end
                S4 : begin 
                            z <= 1; 
                            NS <= x ? S2 : S1 ;
                            $display(PS);
                        end
        default: NS = S0;

            endcase
        end
always @(PS)
begin
  case(PS)
    S4: z = 1;
    default: z = 0;
  endcase 
end 

endmodule

module mooreoutput;
    // Inputs
    reg x;
    reg clk;
    reg reset;
    // Outputs
    wire z;
    // Instantiate the Unit Under Test (UUT)
    seq_detector uut (
        .x(x), 
        .clk(clk), 
        .reset(reset), 
        .z(z)
    );

always #5 clk = ~clk;
    
initial begin
    $dumpfile("mooreoutput.vcd");
    $dumpvars(1,mooreoutput);

    fork
        clk = 1'b0;
        reset = 1'b1;
        #15 reset = 1'b0;
    begin
        #11 x = 0; #10 x = 1 ; #11 x = 1 ; #10 x = 0 ;
        #11 x = 1; #10 x = 1 ; #11 x = 0 ; #10 x = 1 ;
        #11 x = 1; #10 x = 0 ; #11 x = 1 ; #10 x = 1 ;
        #11 x = 0; #10 x = 1 ; #11 x = 1 ; #10 x = 0 ;
        #10 $finish;
        end
        join
end    
endmodule

OUTPUT: enter image description here

The issue is that I have applied 5 times occurring "0110" overlapping, but in the waveform showing output 'z' is occurring 'high' for 4 times . What's the possible modification that I'd have to do, so as to eliminate this error ?can anyone send moore state table and logic circuit of 0110

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2 Answers 2

3
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Adjust the delays on your input in test-bench properly. For the 3rd time the input sequence sampled at pos-edge of clock is 0111 and not 0110. Make sure data is changing before the sampling edge. For debugging you can check the flow of states by dumping the waveforms of all variables with the following verilog syntax.

 $dumpvars();
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  • 1
    \$\begingroup\$ thanks bro I changed the value from #11 to #10 and the waveform shows output 'z' is showing high for 5 times \$\endgroup\$
    – user299749
    Nov 11, 2021 at 6:58
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The problem is that your input x is asynchronous to the clock. You must synchronize it to the clock by driving it in the testbench the same way your design synchronizes to the clock.

Your testbench currently uses # delays and blocking assignments (=).
To guarantee that the simulator will treat the signal as synchronous, you need to use @(posedge clk) and nonblocking assignments (<=).

initial begin
  $dumpfile("mooreoutput.vcd");
  $dumpvars(1,mooreoutput);
  x = 0;
  clk = 1'b0;
  reset = 1'b1;
  #10 reset = 1'b0;
  repeat (1) @(posedge clk); x <= 1;
  repeat (2) @(posedge clk); x <= 0;
  repeat (1) @(posedge clk); x <= 1;
  repeat (2) @(posedge clk); x <= 0;
  repeat (1) @(posedge clk); x <= 1;
  repeat (2) @(posedge clk); x <= 0;
  repeat (1) @(posedge clk); x <= 1;
  repeat (2) @(posedge clk); x <= 0;
  repeat (1) @(posedge clk); x <= 1;
  repeat (2) @(posedge clk); x <= 0;
  repeat (1) @(posedge clk); x <= 1;
  #10 $finish;
end

This shows the z output going high 5 times.

Another benefit to using the clock in the testbench is that, if you change the clock period, you do not need to change all the other # delays in your testbench code.

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