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I am trying to understand the datasheet on Sony ICX404AL CCD sensor and design a small circuit with it. However I am a bit confused with Reset gate and Substrate clock signals.

Information from the datasheet Voltages

Reset gate clock Substrate clock

VϕRG is specified to be 5v input through 0.1uF capacitance. However an example circuit shows that ϕRG pin is also connected to 15V rail through diode and 100k resistor. A similar but different setup can be seen for ϕSUB pin that is connected to Vertical driver CXD1267AN. Datasheet also notes that DC bias for sub is generated inside the CCD. Schematic I would really appreciate if you could help me understand the following points:

  • What is the reason for diode + resistor for ϕRG pin?
  • How is the RG signal transferred through 0.1uF capacitor?
  • How does a setup for ϕSUB pin work and why are additional components configured this way?
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1 Answer 1

Reset to default
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Upon closer consideration of provided table values and waveform it seems that RG pin has following voltage requirements: VRGH = VDD + 0.6 = ~15.6v // High value VRGL = VRGH - VϕRG = VRGH - 5v = ~10.6v // Low value

Therefore answers to my questions are:

  • Capacitor, diode and resistor form a clamper circuit that shifts 0v-5v input to 10v-15v level (still a bit unsure about a difference of 0.6v with table values)
  • The same answer as above
  • For SUB pin the required voltage difference (VϕSUB) is 22v and the output from CXD1267A driver is -8v-15v range. This particular arrangement of components seems to provide the desired waveform: LTSpice

![enter image description here

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